參數(shù)資料
型號(hào)： MAX1359BCTL-T
廠(chǎng)商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
文件頁(yè)數(shù)： 23/74頁(yè)
文件大小： 1214K
代理商： MAX1359BCTL-T
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, CLK32K = 32.768kHz (external clock), CREG = 10F, CCPOUT =
10F, 10F between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25
°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Normal-Mode 60Hz Rejection
Ratio
Data rate = 10sps or 60sps, PGA gain = 1,
unipolar mode (Note 2)
100
dB
Normal-Mode 50Hz Rejection
Ratio
Data rate = 10sps or 50sps, PGA gain = 1,
unipolar mode (Note 2)
100
dB
Absolute Input Range
AGND
AVDD
V
Unipolar mode
-0.05 /
Gain
VREF /
Gain
Differential Input Range
Bipolar mode
-VREF /
Gain
VREF /
Gain
V
ADC not in measurement mode, mux
enabled, TA
≤ +55°C, inputs = +0.1V to
(AVDD - 0.1V)
±1
DC Input Current (Note 7)
TA = +85
°C
±5
nA
Input Sampling Capacitance
CIN
5pF
Input Sampling Rate
fSAMPLE
21.84
kHz
External Source Impedance at
Input
See Table 3
Table 3
k
FORCE-SENSE DAC (MAX1358/MAX1359 only, RL = 10k
and CL = 200pF, FBA = OUTA and FBB = OUTB, unless otherwise
noted)
Resolution
Guaranteed monotonic
10
Bits
Differential Nonlinearity
DNL
Code 3D hex to 3FF hex
±1
LSB
A grade
±2
Integral Nonlinearity
INL
Code 3D hex to 3FF
hex
B grade
±4
LSB
Offset Error
Reference to code 52 hex
±20
mV
Offset-Error Tempco
±4.4
V/
°C
Gain Error
Excludes offset and voltage reference error
±5
LSB
Gain-Error Tempco
Excludes offset and reference drift
±1
ppm/
°C
Input Leakage Current at SWA/B
SWA/B switches open (Notes 7, 8)
±1nA
TA = -40
°C to +85°C
±1nA
TA = 0
°C to +70°C
±600
Input Leakage Current at FBA/B
VFBA/B = +0.3V to
(AVDD - 0.3V)
(Note 7)
TA = 0
°C to +50°C
±400
pA
DAC Output Buffer Leakage
Current
DAC buffer disabled (Note 7)
±75
nA
Input Common-Mode Voltage
At FBA and FBB
0
AVDD -
0.35
V
Line Regulation
AVDD = +1.8V to +3.6V
40
175
V/V
Load Regulation
IOUT =
±2mA, CL = 1000pF (Note 2)
0.5
V/A
Output Voltage Range
AGND
AVDD
V
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