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參數(shù)資料
| 型號(hào)： | MAX1359BCTL-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 32/74頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | MAX1359BCTL-T |
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MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
38
______________________________________________________________________________________
The MUX register configures the positive and negative
mux inputs and can start an ADC conversion.
S (ADR0): Conversion start bit. The S bit is the LSB of
the MUX register address byte. S = 1 resets the regis-
ters inside the ADC filter and initiates a conversion or
calibration. The conversion begins immediately after
the eighth MUX register data bit, when S = 1 and when
writing to the MUX register. This allows the new MUX
and ADC register settings to take effect simultaneously
for a new conversion, if STRT = 0 during the last write
to the ADC register. If the S bit is asserted and the
command is a read from the MUX register, the conver-
sion starts immediately after the S bit (ADR0) is clocked
in by the rising edge of SCLK.
Read the MUX register with S = 1 for the fastest method
of initiating a conversion because only 8 bits are
required. The subsequent MUX register read is valid,
but can be aborted by raising
CS with no harmful side
effects. The initial conversion requires four conversion
cycles for valid output data. If CONT = 0 and S = 1, the
ADC stops after a single conversion and holds the
result in the DATA register. If CONT = 1 and S = 1, the
ADC performs continuous conversions at the rate spec-
ified by the RATE<2:0> bits until CONT deasserts or
ADCE deasserts, powering down the ADC. When a
conversion initiates using the S bit, the STRT bit asserts
and deasserts automatically after the initial conversion
completes. Writing to the MUX register with S = 0 caus-
es the MUX settings to change immediately and the
ADC continues in its prior state with its settings unaf-
fected. When the ADC is powered down, MUX inputs
are open.
MUXP<3:0>: MUX positive input bits. These four bits
select one of ten inputs from the positive MUX to go to the
positive output of the MUX as shown in Table 8. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
MUXN<3:0> MUX negative input bits. These four bits
select one of ten inputs from the negative MUX to go to
the negative output of the MUX as shown in Table 9. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
The DATA register contains the data from the most
recently completed conversion.
MSB
LSB
S (ADR0)
MUXP3
MUXP2
MUXP1
MUXP0
MUXN3
MUXN2
MUXN1
MUXN0
MUX Register (Power-On State: 0000 0000)
POSITIVE MUX INPUT
MAX1358
MAX1359
MAX1360
MUXP3
MUXP2
MUXP1
MUXP0
AIN1
0
SNO1
0
1
FBA
IN3-
0
1
0
SCM1
0
1
FBB
IN2-
0
1
0
SNC1
0
1
0
1
IN1-
0
1
0
TEMP+
0
1
REF
1
0
AGND
1
0
1
101
X
Open
11
X
Table 8. Selecting the Positive MUX Inputs
X = Don’t care.
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