參數(shù)資料
型號(hào)： MAX1359BCTL-T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
文件頁(yè)數(shù)： 43/74頁(yè)
文件大?。?/td> 1214K
代理商： MAX1359BCTL-T
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
48
______________________________________________________________________________________
The PWM_CTRL register contains control bits for the 8-
bit PWM.
PWME: PWM-enable bit. Set PWME = 1 to enable the
internal PWM and set PWME = 0 to disable the internal
PWM. Enable the high frequency clock before enabling
the PWM when using input clock frequencies above
32.768kHz. The power-on default state is 0.
FSEL<2:0>: Frequency selection bits. Selects the PWM
input clock frequency as shown in Table 14. The
power-on default is 000.
SWAH: SWA-switch PWM-high control bit. Set SWAH =
1 to enable the PWM output to directly control the SWA
switch. When SWAH = SWAL, the PWM output is dis-
abled from controlling the SWA switch. When SWAH =
1, a PWM high output closes the SWA switch and a
PWM low output opens the SWA switch. The PWM high
output refers to the beginning of the period when the
output is logic-high. See Table 17 for more details. The
power-on default is 0.
SWAL: SWA-switch PWM-low control bit. Set SWAL = 1
to enable the inverted PWM output to directly control
the SWA switch. When SWAH = SWAL, the PWM output
is disabled from controlling the SWA switch. When
SWAL = 1, a PWM low output closes the SWA switch
and a PWM high output opens the SWA switch. The
PWM low output refers to the end of the period when
the output is logic-low. See Table 17 for more details.
The power-on default is 0.
SWBH: SWB-switch PWM-high control bit. Set SWBH =
1 to enable the PWM output to directly control the SWB
switch. When SWBH = SWBL, the PWM output is dis-
abled from controlling the SWB switch. When SWBH =
1, a PWM high output closes the SWB switch and a
PWM low output opens the SWB switch. The PWM high
output refers to the beginning of the period when the
output is logic-high. See Table 18 for more details. The
power-on default is 0.
SWBL: SWB-switch PWM-low control bit. Set SWBL = 1
to enable the inverted PWM output to directly control
the SWB switch. When SWBH = SWBL the PWM output
is disabled from controlling the SWB switch. When
SWBL = 1, a PWM low output closes the SWB switch
and a PWM high output opens the SWB switch. The
PWM low output refers to the end of the period when
the output is logic-low. See Table 18 for more details.
The power-on default is 0.
SPD1: SPDT1-switch PWM drive control bit. Set SPD1
= 1 to enable the PWM output to directly control the
SPDT1 switch and set SPD1 = 0 to disable the PWM
output controlling the SPDT1 switch. The SPDT1<1:0>
bits, the UPIO pins (if programmed), and the PWM out-
put (if enabled), determine the SPDT1-switch state. See
Table 19 for more details. The power-on default is 0.
SPD2: SPDT2-switch PWM drive control bit. Set SPD2
= 1 to enable the PWM output to directly control the
SPDT2 switch and set SPD2 = 0 to disable the PWM
output controlling the SPDT2 switch. The SPDT2<1:0>
bits, the UPIO pins (if programmed), and the PWM out-
put (if enabled), determine the SPDT2-switch state. See
Table 20 for more details. The power-on default is 0.
MSB
PWME
FSEL2
FSEL1
FSEL0
SWAH
SWAL
SWBH
SWBL
LSB
SPD1
SPD2
X
PWM_CTRL Register (Power-On State: 0000 0000 00XX XXXX)
PWM INPUT FREQUENCY*
(kHz)
FSEL2
FSEL1
FSEL0
4915.2**
0
2457.6**
0
1
1228.8**
0
1
0
32.768
0
1
8.192
1
0
1.024
1
0
1
0.256
1
0
0.032
1
Table 14. Setting the PWM Frequency
*The lower PWM frequencies are useful for power-supply duty
cycling to conserve battery life and enable a single battery cell-
powered system. The higher frequencies allow reasonably small,
external components for RC filtering when used as a DAC for bias
adjustments.
**When the part is in sleep mode, the HFCK is shut down. In this
case, PWM frequencies above 32kHz are not available (see
SPWME in the SLEEP_CFG Register section).
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