參數(shù)資料
型號： MAX1359BCTL-T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
文件頁數(shù)： 40/74頁
文件大?。?/td> 1214K
代理商： MAX1359BCTL-T
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
45
The CLK_CTR register contains the control bits for the
RTC alarms and clocks.
AWE: Alarm write-enable bit. Set AWE = 1 to write data
to the AL_DAY register as well as the ADE bit in this
register. When AWE = 0, all writes are prevented to the
AL_DAY register and the ADE bit in this register. A sec-
ond write to this register is required to change the value
of the ADE bit. The power-on default state is 0.
ADE: Alarm (time-of-day) enable bit. Set ADE = 1 to
enable the time-of-day alarm and set ADE = 0 to dis-
able the time-of-day alarm. When enabled, the ALD bit
in the STATUS register asserts when the RTC second
counter time matches AL_DAY register. The device
wakes up from sleep to normal mode if not already
awake. The ADE bit can only be written if the AWE = 1
from a previous write. The power-on default state is 0.
RWE: RTC write-enable bit. Set RWE = 1 prior to writing
to the RTC register and the RTCE bit in this register. If
RWE = 0, all writes are prevented to the RTC register
as well as the RTCE bit in this register. The RWE signal
takes effect after the rising edge of the 16th clock;
therefore, a second write to this register is required to
change the value of the RTCE bit. The power-on default
state is 0.
RTCE: Real-time-clock enable bit. Set RTCE = 1 to
enable the RTC, and set RTCE = 0 to disable the RTC.
The RTC has a 32-bit second and an 8-bit subsecond
counter. The power-on default state is 1.
OSCE: 32kHz crystal-oscillator enable bit. Set OSCE =
1 to power up the 32kHz oscillator and set OSCE = 0 to
power down the oscillator. The power-on default state
is 1.
FLLE: Frequency-locked-loop enable bit. Set FLLE = 1
to enable the FLL, and set FLLE = 0 to disable the FLL.
If HFCE = 1 and FLLE = 0, the internal high-frequency
oscillator is enabled but it is not frequency-locked to
the 32kHz clock. When FLLE is asserted, it typically
takes 3.5ms for the high-frequency clock to settle to
within 1% of the 32kHz reference clock frequency.
Switching the FLL on or off with this bit does not cause
high-frequency clock glitching. The power-on default
state is 1.
MSB
AWE
ADE
X
RWE
RTCE
OSCE
FLLE
HFCE
LSB
CKSEL2
CKSEL1
CKSEL0
IO32E
CK32E
CLKE
INTP
WDE
CLK_CTRL Register (Power-On State: 00X0 1111 0010 1110)
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