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| 型號： | MAX1359BCTL-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 47/74頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | MAX1359BCTL-T |
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MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
51
The SLEEP_CFG register allows users to program spe-
cific behavior for the 32kHz oscillator, buffer, and PWM
in sleep mode. It also contains a sleep-control bit (SLP)
to enable sleep mode.
SLP (ADR0): Sleep bit. The SLP bit is the LSB in the
SLEEP_CFG address control byte. Set SLP = 1 to
assert the SHDN bit and enter sleep mode. Writing the
register with SLP = 0 or reading with SLP = 0 or SLP =
1 has no effect on the SHDN bit.
SOSCE: Sleep mode 32kHz crystal oscillator enable
bit. SOSCE = 1 enables the 32kHz oscillator in sleep
mode and SOSCE = 0 disables it in sleep mode,
regardless of the state of the OSCE bit. The power-on
default is 1.
SCK32E: Sleep-mode CK32K-pin output-buffer enable
bit. SCK32E = 1 enables the 32kHz output buffer in
sleep mode and SCK32E = 0 disables it in sleep mode,
regardless of the state of the CK32E bit. The power-on
default is 1.
SPWME: Sleep mode PWM enable bit. SPWME = 1
enables the internal PWM in sleep mode and SPWME =
0 disables it in sleep mode, regardless of the state of the
PWME bit.
Input frequencies are limited to 32.768kHz or lower
since the high-frequency clock is disabled in sleep
mode. SOSCE must be asserted to have 32kHz avail-
able as an input to the PWM. The power-on default is 0.
SHDN: Shutdown bit. This bit is read only. SHDN is
asserted by writing to the SLEEP register address or by
writing to the SLEEP_CFG register with SLP = 1. When
SHDN is asserted, the device is in sleep mode even if
the SLEEP or
SLEEP function on the UPIO is deassert-
ed. The SHDN bit is deasserted by writing to the
NORM_MD register or by other defined events. Events
that cause SHDN to be deasserted are a day alarm or
an edge on the UPIO wake-up pin causing wake-up to
be asserted. The power-on default is 0.
MSB
LSB
SLP (ADR0)
SOSCE
SCK32E
SPWME
SHDN
X
SLEEP_CFG Register (Power-On State: 1100 XXXX)
4Hz CLOCK
2-BIT COUNTER
X
WDE = 1
01
2
3
RESET
WATCHDOG
ADDRESS
01
2
WATCHDOG
ADDRESS
WATCHDOG
ADDRESS
01
0
1
2
0
750ms
250ms
SPI WRITES
D
Q
R
CK
DQ
Q
R
CK
DIVIDE-
BY-8192
32K
WDE
POR
WDW
WATCHDOG TIMER
4Hz
RESET
Figure 19. Watchdog Timer Architecture
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