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| 型號： | MAX1359BCTL-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 55/74頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | MAX1359BCTL-T |
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MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
59
nominally and the rising threshold is +2.0V nominally. The
hysteresis helps eliminate chatter when running directly off
unregulated batteries. If DVDD falls below +1.3V (typ), the
power-on reset circuitry is enabled and the HYSE bit is
deasserted setting the hysteresis back to +20mV. The
power-on default is 0.
RSTE:
RESET output enable bit. Set RSTE = 1 to
enable
RESET to be controlled by the +1.8V DVDD low-
supply-voltage detector and set RSTE = 0 to disable
this control. The power-on default is 1.
The STATUS register contains the status bits of events in
various system blocks. Any status bits not masked in the
IMSK register cause an interrupt on INT. Some of the
status bit setting events (GPI, WAKEUP, ALARM, DRDY)
can be directed to UPIO_ to provide multiple C inter-
rupt inputs. There are no specific mask bits for the UPIO
interrupt signals since the bits are effectively masked by
selecting a different function for UPIO. The STATUS bits
always record the triggering event(s), even for masked
bits, which do not generate an interrupt on INT. It is pos-
sible to set multiple STATUS bits during a single INT
interrupt event. Clear all status bits except for ADD and
ADOU by reading the STATUS register. During a STA-
TUS register read, INT deasserts when the first STATUS
data bit (LDVD) reads out (9th rising SCLK) and remains
deasserted until shortly after the last STATUS data bit
(~15ns). At this point, INT reasserts if any status bit is set
during the STATUS register read. If the STATUS register
is partially read (i.e., the read is aborted midway), none
of the status bits are cleared. New events occurring dur-
ing a STATUS register read, or events that persist after
reading the STATUS bits result in another interrupt
immediately after the STATUS register read finishes. This
is a read-only register.
LDVD: Low DVDD voltage-detector status bit. LDVD = 1
indicates DVDD is below the +1.8V threshold, otherwise
LDVD = 0. LDVD clears during the STATUS register
read as long as the condition does not persist.
Otherwise, the LDVD bit reasserts immediately. If the
DVDD low voltage detector is disabled, LDVD = 0. The
power-on default is 0.
LCPD: Low CPOUT voltage-detector status bit. LCPD =
1 indicates CPOUT is below the +2.7V threshold, other-
wise LCPD = 0. LCPD clears during the STATUS regis-
ter read as long as the condition does not persist.
Otherwise the LCPD bit reasserts immediately. LCPD =
0 when the CPOUT low voltage detector is disabled.
The power-on default is 0.
ADOU: ADC overflow/underflow status bit. ADOU = 1
indicates an ADC underflow or overflow condition in the
current ADC result. New conversions that are valid
clear the ADOU bit. ADOU = 0 when the ADC data is
valid or the ADC is disabled (ADCE = 0). An underflow
condition occurs when the ADC data is theoretically
less than 0000 hex in unipolar mode and less than
8000 hex in bipolar mode. An overflow condition occurs
when the ADC data is theoretically greater than FFFF
hex in unipolar mode and greater than 7FFF hex in
bipolar mode. Use this bit to determine the validity of
an ADC result at the maximum or minimum code values
(i.e., 0000 hex or FFFF hex for unipolar mode and 8000
hex and 7FFF hex for bipolar mode). The power-on
default is 0. Reading the STATUS register does not
clear the ADOU bit.
SDC: Signal-detect comparator status bit. When SDC =
1, the positive input to the signal-detect comparator
exceeds the negative input plus the programmed thresh-
old voltage. The SDC bit clears during the STATUS regis-
ter read unless the condition remains true. The SDC bit
also deasserts when the signal-detect comparator pow-
ers down (SDCE = 0). The power-on default is 0.
CRDY: High-frequency-clock ready status bit. CRDY =
1 indicates a locked high-frequency clock to the 32kHz
reference frequency by the FLL. The CRDY bit clears
during the STATUS register read. This bit only asserts
after power-up or after enabling the FLL using the FLLE
bit. The power-on default is 0.
ADD: ADC-done status bit. ADD = 1 indicates a com-
pleted ADC conversion or calibration. Clear the ADD bit
by reading the appropriate ADC data, offset, or gain-cali-
bration registers. The ADC status bit also clears when a
new ADC result updates to the data or calibration regis-
ters (i.e., it follows the assertion level of the UPIO =
DRDY signal). Reading the STATUS register does not
clear this bit. This bit is equivalent to the DRDY signal
available through UPIO_. The power-on default is 0.
MSB
LDVD
LCPD
ADOU
SDC
CRDY
ADD
ALD
X
LSB
UPR4
UPR3
UPR2
UPR1
UPF4
UPF3
UPF2
UPF1
STATUS Register (Power-On State: 0000 000X 0000 0000)
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