參數(shù)資料
型號(hào)： MAX1359BCTL-T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
文件頁(yè)數(shù)： 39/74頁(yè)
文件大?。?/td> 1214K
代理商： MAX1359BCTL-T
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
44
______________________________________________________________________________________
MSB
ASEC19
ASEC18
ASEC17
ASEC16
ASEC15
ASEC14
ASEC13
ASEC12
ASEC11
ASEC10
ASEC9
ASEC8
ASEC7
ASEC6
ASEC5
ASEC4
LSB
ASEC3
ASEC2
ASEC1
ASEC0
X
AL_DAY Register (Power-On State: 0000 0000 0000 0000 0000 XXXX)
The AL_DAY register stores the second information of
the time-of-day alarm.
ASEC<19:0>: Alarm-second bits. These 20 bits store
the time-of-day alarm, which corresponds to the lower
20 bits of the RTC second counter or SEC<19:0>.
Program the time-of-day alarm trigger between 1s to
just over 12 days beyond the current RTC second
counter value in increments of 1s.
Assert the AWE bit in the CLK_CTRL register (see the
CLK_CTRL Register section) to enable writing to the
AL_DAY register. Enabling the time-of-day alarm requires
two writes to the CLK_CTRL register. Write the 20 alarm-
second bits in 3 bytes, MSB first. If
CS is raised before
the LSB is written, the alarm write is aborted, and the
existing value remains. When the lower 20 bits in the RTC
second counter match the contents of this register, the
alarm triggers and asserts ALD in the STATUS register. It
also asserts an interrupt on the INT pin unless masked by
the MALD bit in the IMSK register. The part enters normal
mode if an alarm triggers while in sleep mode. The time-
of-day alarm is intended to trigger single events.
Therefore, once it triggers, in the CLK_CTRL register, the
ADE bit is automatically cleared, disabling the time-of-
day alarm. Implement a recurring alarm with repeated
software writes over the serial interface each time the
time-of-day alarm triggers. The time-of-day alarm can
also be programmed to output at the UPIO pins.
When configured this way the MALD bit does not mask
the UPIO alarm output.
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