參數(shù)資料
型號(hào)： MAX1359BCTL-T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC40
封裝： 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40
文件頁數(shù)： 59/74頁
文件大?。?/td> 1214K
代理商： MAX1359BCTL-T
MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
62
______________________________________________________________________________________
With the SHDN bit = 0, deassert the SLEEP or
SLEEP function on UPIO, only if SLEEP or SLEEP
function is used for entering sleep mode.
With the SLEEP or
SLEEP function deasserted on
UPIO, clear the SHDN bit by writing to the normal-
mode register address control byte.
With the SLEEP or
SLEEP function deasserted,
assert WU or
WU (wake-up) function on UPIO.
With the SLEEP or
SLEEP function deasserted, the
day alarm triggers.
Wake-Up
A wake-up event, such as an assertion of a UPIO con-
figured as WU or a time-of-day alarm causes the
MAX1358/MAX1359/MAX1360 to exit sleep mode, if in
sleep mode. A wake-up event in normal mode results
only in a wake-up event being recorded in the
STATUS register.
RESET
The
RESET output pulls low for any one of the following
cases: power-on reset, DVDD monitor trips and RSTE =
0, watchdog timer expires, crystal oscillator is attached,
and 32kHz clock not ready.
The
RESET output can be turned off through the RSTE
bit in the PS_VMONS register, causing DVDD low sup-
ply voltage events to issue an interrupt or poll through
the LDVD status bit. This allows brownout detection
Cs that operate with DVDD < 1.8V.
Driving UPIO Outputs to AVDD Levels
UPIO outputs can be driven to AVDD levels in systems
with separate AVDD and DVDD supplies. Disable the
charge-pump doubler by setting CPE = 0 in the
PS_VMONS register, and connect the system’s analog
supply to AVDD and CPOUT. Setting UPIO outputs to
drive to CPOUT results in AVDD-referenced logic levels.
Supply Voltage Measurement
The AVDD supply voltage can be measured with the
ADC by reversing the normal input and reference sig-
nals. The REF voltage is applied to one multiplexer
input and AGND is selected in the other. The AVDD sig-
0000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0010
65,535
65,533
INPUT VOLTAGE (LSB)
BI
N
A
RY
O
U
TP
UT
CO
DE
1111 1111 1111 1101
1111 1111 1111 1110
1111 1111 1111 1111
1 LSB =
VREF
(GAIN x 65,536)
0
2
VREF/GAIN
V
REF
/GAIN
13
1111 1111 1111 1100
0000 0000 0000 0011
FULL-SCALE TRANSITION
Figure 22. ADC Unipolar Transfer Function
0+1
-1
1000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0010
+32,767
+32,765
INPUT VOLTAGE (LSB)
BI
N
A
R
Y
O
U
TP
U
T
CO
DE
0111 1111 1111 1101
0111 1111 1111 1110
0111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0001
1111 1111 1111 1111
1 LSB =
VREF
(GAIN x 65,536)
x 2
-32,768
-32,766
VREF/GAIN
V
REF
/GAIN
V
REF
/GAIN
Figure 23. ADC Bipolar Transfer Function
MAX1358
MAX1359
DAC A
OUTA
OUTB
THE MAX1359 HAS ONE DAC.
REF
DAC B
FBA
FBB
Figure 24. DAC Unipolar Output Circuit
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