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參數(shù)資料
| 型號(hào)： | MAX1359BCTL-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 44/74頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | MAX1359BCTL-T |
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MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
49
MSB
PWMTH7
PWMTH6
PWMTH5
PWMTH4
PWMTH3
PWMTH2
PWMTH1
PWMTH0
LSB
PWMTP7
PWMTP6
PWMTP5
PWMTP4
PWMTP3
PWMTP2
PWMTP1
PWMTP0
PWM_THTP Register (Power-On State: 0000 0000 0000 0000)
The PWM_THTP register contains the bits that set the
PWM on-time and period.
PWMTH<7:0>: PWM time high bits. These bits define
the PWM on (or high) time and when combined with the
PWMTP<7:0> bits, they determine the duty cycle and
period. The on-time duty cycle is defined as:
(PWMTH<7:0> + 1) / (PWMTP<7:0> + 1)
To get 50% duty cycle, set PWMTH<7:0> to 127 deci-
mal and PWMTP<7:0> to 255 decimal. A 100% duty
cycle (i.e., always on) is possible with a value of
PWMTH<7:0>
≥ PWMTP<7:0> > 0. A 0% duty cycle is
possible by setting PWMTH<7:0> = 0 or PWME = 0 in
the PWM_CTRL register. If the PWM is selected to drive
the UPIO_ pin(s), the ALH_ bit(s) (UPIO_CTRL register)
determine the on-time polarity at the beginning of the
PWM cycle. If ALH_= 1, the on-time at the start of the
PWM period causes a logic-high level (DVDD or
CPOUT) at the UPIO_ pin and when ALH_= 0, it causes
a logic-low level (DGND) during the on-time. When the
PWM output drives the SWA/B switches, the SWA(B)H
or SWA(B)L bits in the PWM_CTRL register, determine
which PWM phase closes these switches. The SPDT1
and SPDT2 switches do not have PWM polarity inver-
sion bits (see the SPDT1<1:0> and SPDT2<1:0> bit
descriptions in the SW_CTRL Register section) but their
effective polarity is set by how the switches are con-
nected externally. The power-on default is 00 hex.
PWMTP<7:0>: PWM time period bits. These bits con-
trol the PWM output period defined. The PWM output
period is defined as:
(PWMTP<7:0> + 1) / (PWM input frequency)
Set the PWM input frequency by selecting the
FSEL<2:0> bits as described in Table 14. The power-
on default is 00 hex.
WATCHDOG Register (Power-On State: N/A)
Writing to the WATCHDOG register address sets the
watchdog timer to 0ms. If the watchdog is enabled
(WDE = 1) and the WATCHDOG register is not written
to before the 750ms expiration,
RESET asserts low for
250ms and the watchdog timer restarts at 0ms when
the watchdog timer is enabled. There are no data bits
for this register and the watchdog timer is reset on the
rising edge of SCLK during the ADR0 bit in the
WATCHDOG register address control byte. Figure 19
shows an example of watchdog timing.
NORM_MD Register (Power-On State: N/A)
Exit sleep mode and enter normal mode by writing to
the NORM_MD register. The specific normal-mode
state of all circuit blocks is set by the user, who must
configure the individual power-enable bits before enter-
ing sleep mode (Table 15). There are no data bits for
this register and normal mode begins on the rising
edge of SCLK during the ADR0 bit in the NORM_MD
register address control byte.
SLEEP Register (Power-On State: N/A)
Enter sleep mode by writing to the SLEEP register. This
low-power state overrides most of the normal power-
control bits. Table 15 shows which functions are off,
which functions are unaffected (ADE, RTCE, LSDE, and
HYSE), and which functions are controlled by special
sleep-mode bits (SOSCE, SCK32E, and SPWME) while
in sleep mode. There are no data bits for this register
and sleep mode begins on the rising edge of SCLK
during the ADR0 bit in the SLEEP register address con-
trol byte.
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