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參數資料
| 型號： | MAX1359BCTL-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數： | 57/74頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | MAX1359BCTL-T |
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MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
60
______________________________________________________________________________________
ALD: Alarm (day) status bit. ALD = 1 when the value
programmed in ASEC<19:0> in the AL_DAY register
matches SEC<19:0> in the RTC register. Clear the ALD
bit by reading the STATUS register or by disabling the
day alarm (ADE = 0). The power-on default is 0.
UPR<4:1>: User-programmable I/O rising-edge status
bits. UPR_ = 1 indicates a rising edge on the respec-
tive UPIO_ pin has occurred. Clear UPR_ by reading
the STATUS register. Rising edges are detected inde-
pendent of UPIO_ configuration, providing the ability to
capture and record rising input (e.g., WU) or output
(e.g., PWM) edge events on the UPIO_. Set the appro-
priate mask to determine if the edge will generate an
interrupt on INT. If the UPIO_ is configured as an out-
put, INT provides confirmation that an intended rising
edge output occurred and has reached the desired
DVDD or CPOUT level (i.e., was not loaded down exter-
nally). The power-on default is 0.
UPF<4:1>: User-programmable I/O falling-edge status
bit. UPF_= 1 indicates a falling edge on the respective
UPIO_ has occurred. Clear UPF_ by reading the
STATUS register. Falling edges are detected indepen-
dent of UPIO_ configuration, providing the ability to cap-
ture and record falling input (e.g., WU) or output (e.g.,
PWM) edge events on the UPIO_. Set the appropriate
mask to determine if that edge should generate an inter-
rupt on the INT pin. If the UPIO is configured as an out-
put, the INT provides confirmation that an intended
falling edge output occurred at the pin and it reached
the desired DGND level. The power-on default is 0.
Applications Information
Analog Filtering
The internal digital filter does not provide rejection
close to the harmonics of the modulator sample fre-
quency. However, due to high oversampling ratios in
the MAX1358/MAX1359/MAX1360, these bands typical-
ly occupy a small fraction of the spectrum and most
broadband noise is filtered. Therefore, the analog filter-
ing requirements in front of the MAX1358/MAX1359/
MAX1360 are considerably reduced compared to a
conventional converter with no on-chip filtering. In addi-
tion, because the device’s common-mode rejection
(60dB) extends out to several kHz, the common-mode
noise susceptibility in this frequency range is substan-
tially reduced.
Depending on the application, provide filtering prior to the
MAX1358/MAX1359/MAX1360 to eliminate unwanted fre-
quencies the digital filter does not reject. Providing addi-
tional filtering in some applications ensures that
differential noise signals outside the frequency band of
interest do not saturate the analog modulator.
When placing passive components in front of the
MAX1358/MAX1359/MAX1360, ensure a low enough
source impedance to prevent introducing gain errors to
the system. This configuration significantly limits the
amount of passive anti-aliasing filtering that can be
applied in front of the MAX1358/MAX1359/MAX1360.
See Table 3 for acceptable source impedances.
Power-On Reset or Power-Up
After a power-on reset, the DVDD voltage supervisor is
enabled and all UPIOs are configured as inputs with
pullups enabled. The internal oscillators are enabled
and are output at CLK and CLK32K once the DVDD
voltage supervisor is cleared and the subsequent time-
out period has expired. All interrupts are masked
except CRDY. Figure 21 illustrates the timing of various
signals during initial power-up, sleep mode, and wake-
up events. The ADC, charge pump, internal reference,
op amp(s), DAC(s), and switches are disabled after
power-up.
Power Modes
Two power modes are available for the MAX1358/
MAX1359/MAX1360; sleep and normal mode. In sleep
mode, all functional blocks are powered down except
the serial interface, data registers, internal bandgap,
wake-up circuitry (if enabled), DVDD voltage supervisor
(if enabled), and the 32kHz oscillator (if enabled),
which remain active. See Table 15 for details of the
sleep-mode and normal-mode power states of the vari-
ous internal blocks.
Each analog block can be shut down individually
through its respective control register with the excep-
tion of the bandgap reference.
Sleep Mode
Sleep mode is entered one of three ways:
Writing to the SLEEP register address. The result is
the SHDN bit is set to 1.
Asserting the SLEEP or
SLEEP function on a UPIO
(SLEEP takes precedence over software writes or
wake-up events). The SHDN bit is unaffected.
Asserting the SHDN bit by writing SLP = 1 in the
SLEEP_CFG register.
Entering sleep mode is an OR function of the UPIO or
SHDN bit. Before entering sleep mode, configure the
normal mode conditions.
Exit sleep mode and enter normal mode by one of the
following methods:
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