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| 型號： | MAX1359BCTL-T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, MO220, TQFN-40 |
| 文件頁數(shù)： | 65/74頁 |
| 文件大小： | 1214K |
| 代理商： | MAX1359BCTL-T |
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MAX1358/MAX1359/MAX1360
16-Bit Data-Acquisition Systems with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
68
______________________________________________________________________________________
ADC Calibration
Internal to the MAX1358/MAX1359/MAX1360, the ADC
is 24 bits and is always in bipolar mode. The OFFSET
CAL and GAIN CAL data are also 24 bits. The conver-
sion to unipolar and the gain are performed digitally.
The default values for the OFFSET CAL and GAIN CAL
registers in the MAX1358/MAX1359/MAX1360 are
00 0000h and 80 0000h, respectively.
The calibration works as follows:
ADC = (RAW - OFFSET) x Gain x PGA
where ADC is the conversion result in the DATA regis-
ter, RAW is the output of the decimation filter internal to
the MAX1358/MAX1359/MAX1360, OFFSET is the value
stored in the OFFSET CAL register, Gain is the value
stored in the GAIN CAL register, and PGA is the select-
ed PGA gain found in the ADC register as GAIN<1:0>.
In unipolar mode, all negative values return a zero
result and an additional gain of 2 is added.
For self-calibration, the offset value is the RAW result
when the inputs are shorted internally and the gain value
is 1 / (RAW - OFFSET) with the reference connected to
the input. This is done automatically when these modes
are selected. The self offset and gain calibration corrects
for errors internal to the ADC and the results are stored
and used automatically in the OFFSET CAL and GAIN
CAL registers. For best results, use the ADC in the same
configuration as the calibration. This pertains to conver-
sion rate only because the PGA gain and unipolar/bipo-
lar modes are performed digitally.
For system calibration, the offset and gain values cor-
rect for errors in the whole signal path including the
internal ADC and any external circuits in the signal
path. For the system calibration, a user-provided zero-
input condition is required for the offset calibration and
a user-provided full-scale input is required for the gain
calibration. These values are automatically written to
the OFFSET CAL and GAIN CAL registers. The order of
the calibrations should be offset followed by gain.
The offset correction value is in two’s complement. The
default value is 000000h, 00...00b, or 0 decimal.
The gain correction value is an unsigned binary num-
ber with 23 bits to the right of the decimal point. The
largest number is therefore 1.1111...1b = 2 - 2-23 and
the smallest is 0.000...0b = 0, although it does not
make sense to use a number smaller than 0.1000...0b
= 0.5. The default value is 800000h, 1.000...0b or 1
decimal.
Changing the offset or gain calibration values does not
affect the value in the DATA register until a new conver-
sion has completed. This applies to all the mode bits
for PGA gain, unipolar/bipolar, etc.
Grounding and Layout
For best performance, use PC boards with separate
analog and digital ground planes.
Design the PC board so that the analog and digital sec-
tions are separated and confined to different areas of
the board. Join the digital and analog ground planes at
one point. If the DAS (MAX1358/MAX1359/MAX1360) is
the only device requiring an AGND-to-DGND connec-
tion, connect planes to the AGND pin of the DAS. In
systems where multiple devices require AGND-to-
DGND connections, the connection should still be
made at only one point. Make the star ground as close
to the MAX1358/MAX1359/MAX1360 as possible.
Avoid running digital lines under the device because
these may couple noise onto the device. Run the ana-
log ground plane under the MAX1358/MAX1359/
MAX1360 to minimize coupling of digital noise. Make
the power-supply lines to the MAX1358/MAX1359/
MAX1360 as wide as possible to provide low-imped-
ance paths and reduce the effects of glitches on the
power-supply line.
Shield fast-switching signals such as clocks with digital
ground to avoid radiating noise to other sections of the
board. Avoid running clock signals near the analog
inputs. Avoid crossover of digital and analog signals.
Good decoupling is important when using high-resolu-
tion ADCs. Decouple all analog supplies with 10F
capacitors in parallel with 0.1F HF ceramic capacitors
to AGND. Place these components as close to the
device as possible to achieve the best decoupling.
Crystal Layout
Follow basic layout guidelines when placing a crystal
on a PC board with a DAS to avoid coupled noise.
1) Place the crystal as close as possible to 32KIN and
32KOUT. Keeping the trace lengths between the
crystal and inputs as short as possible reduces the
probability of noise coupling by reducing the length
of the “antennae”. Keep the 32KIN and 32KOUT
lines close to each other to minimize the loop area
of the clock lines. Keeping the trace lengths short
also decreases the amount of stray capacitance.
2) Keep the crystal solder pads and trace width to
32KIN and 32KOUT as small as possible. The larg-
er these bond pads and traces are, the more likely
it is that noise will couple from adjacent signals.
3) Place a guard ring (connect to ground) around the
crystal to isolate the crystal from noise coupled
from adjacent signals.
4) Ensure that no signals on other PC board layers run
directly below the crystal or below the traces to
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