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參數(shù)資料
| 型號： | WEDPNF8M721V-1012BC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 686K |
| 代理商： | WEDPNF8M721V-1012BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
Parameter
Symbol
-100
-125
Unit
Min
Max
Min
Max
Access time from CLK (pos. edge)
CL = 3
tAC
66
ns
CL = 2
tAC
6—
ns
Address hold time
tAH
11
ns
Address setup time
tAS
22
ns
CLK high-level width
tCH
33
ns
CLK low-level width
tCL
33
ns
Clock cycle time (6)
CL = 3
tCK
88
ns
CL = 2
tCK
10
—
ns
CKE hold time
tCKH
11
ns
CKE setup time
tCKS
22
ns
CS, RAS, CAS, WE, DQM hold time
tCMH
11
ns
CS, RAS, CAS, WE, DQM setup time
tCMS
22
ns
Data-in hold time
tDH
11
ns
Data-in setup time
tDS
22
ns
Data-out high-impedance time
CL = 3 (7)
tHZ
66
ns
CL = 2 (7)
tHZ
7—
ns
Data-out low-impedance time
tLZ
11
ns
Data-out hold time (load)
tOH
33
ns
Data-out hold time (no load) (8)
tOHN
1.8
ns
ACTIVE to PRECHARGE command
tRAS
50
120,000
45
120,000
ns
ACTIVE to ACTIVE command period
tRC
70
68
ns
ACTIVE to READ or WRITE delay
tRCD
20
ns
Refresh period (4,096 rows) – Commercial, Industrial
tREF
64
ms
Refresh period (4,096 rows) – Military
tREF
16
—
ms
AUTO REFRESH period
tRFC
70
—
ns
PRECHARGE command period
tRP
20
ns
ACTIVE bank A to ACTIVE bank B command
tRRD
15
16
ns
Transition time (9)
tT
0.3
1.2
0.3
1.2
ns
WRITE recovery time
(10)
tWR
1 CLK + 7ns
—
(11)
15
ns
Exit SELF REFRESH to ACTIVE command
tXSR
80
78
ns
SDRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(Notes 1, 2, 3, 4, 5)
NOTES:
1. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range is ensured.
2. An initial pause of 100ms is required after power-up, followed by two
AUTO REFRESH commands, before proper device operation is ensured.
(VCC must be powered up simultaneously.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh require-
ment is exceeded.
3. In addition to meeting the transition rate specification, the clock and CKE
must transit between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
4. Outputs measured at 1.5V with equivalent load:
5. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced
to 1.5V crossover point.
6. The clock frequency must remain constant (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin)
during access or precharge states (READ, WRITE, including tWR, and
PRECHARGE commands). CKE may be used to reduce the data rate.
7. tHZ defines the time at which the output achieves the open circuit
condition; it is not a reference to VOH or VOL. The last valid data element
will meet tOH before going High-Z.
8. Guaranteed by design, but not tested.
9. AC characteristics assume tT = 1ns.
10. Auto precharge mode only. The precharge timing budget (tRP) begins
7.5ns/7ns after the first clock delay, after the last WRITE is executed.
11. Precharge mode only.
Q
50pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1012BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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