參數(shù)資料
型號(hào)： WEDPNF8M721V-1012BC
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 13/42頁(yè)
文件大?。?/td> 686K
代理商： WEDPNF8M721V-1012BC
20
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
FLASH COMMAND DEFINITIONS
Writing specific address and data commands or sequences into
the command register initiates device operations. Table 7 defines
the valid register command sequences. Writing incorrect ad-
dress and data values or writing them in improper se-
quence will reset the device to the read array data.
All addresses are latched on falling edge of FWE or FCS, which-
ever occurs later. All data is latched on the rising edge of FWE or
FCS, whichever occurs first. Refer to the appropriate timing
diagrams in the “Flash AC Characteristics” section.
READ ARRAY DATA
Upon initial device power-up the device defaults to read array
data. No commands are required to retrieve data. The device is
also ready to read array data after it has completed an Embedded
Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device
enters the Erase Suspend mode. The system can read array data
using the standard read timings, except that if it reads at an
address within erase-suspend sectors, the device outputs status
data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with
the same exception. See “Erase Suspend/Erase Resume Com-
mands” for more information on this mode.
The system
must issue the reset command to re-enable the device
for reading array data if FD5 goes high, or while in the autoselect
mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” on the “Bus
Operations” section for more information. The Data Sheet Read
Operations table provides the read parameters, and the Read
Operations Timing Diagram shows the timing diagram.
RESET COMMAND
Writing the reset command to the device resets the device to
reading array data. Address bits are “don't care” for this com-
mand.
The reset command may be written between the sequence cycles
in an erase command sequence before erasing begins. This resets
the device to reading array data. Once erasure begins, however,
the device ignores reset commands until the operation is com-
plete.
The reset command may be written between the sequence cycles
in a program command sequence before programming begins.
This resets the device to reading array data (also applies to
programming in Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the operation
is complete.
The reset command may be written between the sequence cycles
in an autoselect command sequence. Once in autoselect mode,
the reset command
must be written to return to reading array data
(also applies to autoselect during Erase Suspend mode).
If FD5 goes high during a program or erase operation, writing the
reset command returns the device to reading array data (also
applies during Erase Suspend).
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or
words to the device faster than using the standard program
command sequence. The unlock bypass command sequence is
initiated by first writing two unlock cycles. This is followed by a
third write cycle containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required to
program in this mode. The first cycle in this sequence contains the
unlock bypass program command, A0h; the second cycle contains
the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock
cycles required in the standard program command sequence,
resulting in fast total programming time. Table 7 shows the
requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program
and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass
reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are “don't care” for
both cycles. The device then returns to reading array data.
Figure 6 illustrates the algorithm for the program operation. See
the Erase/Program Operations table in the “Flash AC Characteristics”
for parameters, and to Figure 12 for timing diagrams.
Autoselect Command Sequence
The autoselect command sequence allows the host system to
determine whether or not a sector is protected. Table 7 shows the
address and data requirements. This method is an alternative to
that shown in Table 6, which is intended for PROM programmers
and requires VID on address bit FA9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The device
then enters the autoselect mode, and the system may read at any
address any number of times, without initiating another command
sequence.
A read cycle containing a sector address (SA) and the address 02h
in word mode (or 04h in byte mode) returns 02h in that sector is
protected, or 00h if it is unprotected. Refer to Table 5 for valid
sector addresses.
The system must write the reset command to exit autoselect mode
and return to reading array data.
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