參數(shù)資料
型號(hào)： WEDPNF8M721V-1012BC
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 18/42頁(yè)
文件大?。?/td> 686K
代理商： WEDPNF8M721V-1012BC
25
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write
operation: FD2, FD3, FD5, FD6, and FD7. Table 8 and the following
subsections describe the functions of these bits. FD7, RY/BY1, and
FD6 each offer a method for determining whether a program or
erase operation is complete or in progress. These bits are dis-
cussed first.
FD7: Data Polling
The Data Polling bit, FD7, indicates to the host system whether an
Embedded Algorithm is in progress or completed, or whether the
device is in Erase Suspend Data Polling valid after the rising edge
of the final FWE pulse in the program or erase command se-
quence.
During the Embedded Program algorithm, the device outputs on
FD7 the complement of the datum programmed to FD7. This FD7
status also applies to programming during Erase Suspend. When
the Embedded Program algorithm is complete, the device outputs
the datum programmed to FD7. The system must provide the
program address to read valid status information on FD7. If a
program address falls within a protected sector, Data Polling on
FD7 is active for approximately 1
s, then the device returns to
reading array data.
During the Embedded Erase algorithm, Data Polling produces a
“0” on FD7. When the Embedded Erase algorithm is complete, or
if the device enters the Erase Suspend mode, Data Polling pro-
duces a “1” on FD7. This analogous to the complement/true datum
output described for the Embedded Program algorithm: the erase
function changes all the bits in a sector to “1”; prior to this, the
device outputs the “complement,” or “0.” The system must pro-
vide an address within any of the sectors selected for erasure to
read valid status information on FD7.
After an erase command sequence is written, if all sectors se-
lected for erasing are protected, Data Polling on FD7 is active for
approximately 100
s, then the device returns to reading array
data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects FD7 has changed from the complement
to true data, it can read valid data at FD7-0 on the
following read
cycles. This because FD7 may change asynchronously with FD0-6
while Flash Output Enable (FOE) is asserted low. Figure 14, Data
Polling timings (During Embedded algorithms), in the “Flash AC
characteristics” section illustrates this.
Table 8 shows the outputs for Data Polling on FD7. Figure 8 shows
the Data Polling algorithm.
FIG. 8
DATA POLLING ALGORITHM
1. FD7 should be rechecked even if FD5 = 1 because FD7 may change
simultaneously with FD5.
Start
Read Byte
(FD0-FD7)
Addr = VA
Read Byte
(FD0-FD7)
Addr = VA
Fail
FD7 = Data
?
FD5 = 1
?
FD7 = Data
?
No
Yes
No
Pass
No
VA = Byte address for programming
= Any of the sector addresses within the
sector being erased during sector erase
operation
= Valid address equals any non-protected
sector group address during chip erase
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