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參數(shù)資料
| 型號(hào)： | WEDPNF8M721V-1012BC |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 14/42頁 |
| 文件大?。?/td> | 686K |
| 代理商： | WEDPNF8M721V-1012BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on
the state of the BYTE1 pin. Programming is a four-bus-cycle
operation. The program command sequence is initiated by writing
two unlock write cycles, followed by the program set-up command.
The program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timing. The device automatically
provides internally generated program pulses and verifies the
programmed cell margin. Table 7 shows the address and data
requirements for the byte program command sequence.
When the Embedded program algorithm is complete, the device
then returns to reading array data and addresses are no longer
latched. The system can determine the status of the program
operation by using FD7, FD6, or RY/BY1. See “Write Operation
Status” for information on these status bits.
Any
commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The program
command sequences should be reinitiated once the device has
reset to reading array data, to ensure date integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to
a “1”. Attempting to do so may halt the operation and set FD5 to
“1”, or cause the Data Polling algorithm to indicate the operation
was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0” to a “1”.
CHIP ERASE COMMAND SEQUENCE
Chip erase is six bus cycle operation. The chip erase command
sequence is initiated by writing two unlock cycles, followed by a
setup command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does
not require the
system to preprogram prior to erase. The Embedded Erase algorithm
automatically programs and verifies the entire memory for an all
zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations.
Table 7 shows the address and data requirements for the chip
erase command sequence.
Any commands written to the chip during the Embedded Erase
algorithm are ignored. Note that a hardware reset during the
chip erase operation immediately terminates the operation. The
Chip Erase command sequence should be re-initiated once the
device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by
using FD7, FD6, or FD2, or RY/BY1. See “Write Operation Status”
for information on these status bits. When the Embedded Erase
algorithm is complete, the device returns to reading array data
FIG. 6
PROGRAM OPERATION
Start
Write Program
Command Sequence
Data Poll from System
Programming Completed
No
Increment
Address
Last Address
?
No
Verify Data?
Yes
Embedded
Program
Algorithm
in progress
NOTE: See Table 7 for program command sequence.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M721V-1012BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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