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參數資料
| 型號： | WEDPNF8M721V-1012BC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數： | 20/42頁 |
| 文件大小： | 686K |
| 代理商： | WEDPNF8M721V-1012BC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
FD5: Exceeded Timing Limits
FD5 will indicate whether the program or erase time has exceeded
the specified limits (internal pulse count). Under these conditions
FD5 will produce a “1”. This is a failure condition that indicates the
program or erase cycle was not successfully completed.
The FD5 failure condition may appear if the system tries to
program a “1” to a location that is previously programmed to “0.”
Only an erase operation can change a “0” back to a “1.” Under this
condition, the device halts the operation, and when the operation
has exceeded timing limits, the FD5 bit will produce a “1”.
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
FD3: Sector Erase Timer
After writing a sector erase command sequence, the system may
read FD3 to determine whether or not an erase operation has
begun. (The sector erase timer does not apply to the chip erase
command.) If additional sectors are selected for erasure, the
entire time-out also applies after each additional sector erase
command. When the time-out is completed, FD3 switches from
“0” to “1.” The system may ignore FD3 if the system can guarantee
that the time between additional sector erase commands will
always be less than 50
s. See also the “Sector Command Se-
quence” section.
After the sector erase command sequence is written, the system
should read the status on FD7 (Data Polling) or FD6 (Toggle Bit I) to
ensure the device has accepted the command sequence, and then
read FD3. If FD3 is high (“1”) the internally controlled erase cycle
has begun; all further commands (other than Erase Suspend) will
be ignored until the erase operation is completed. If FD3 is low
(“0”), the device will accept additional sector erase commands. To
ensure the command has been accepted, the system software
should check the status of FD3 prior to and following each subse-
quent sector erase command. If FD3 is high on the second status
check, the last command may not have been accepted. Table 8
shows the outputs for FD3.
FIG. 9
TOGGLE BIT ALGORITHM
1. Read toggle bit twice to detemine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as FD5 changes to 1. See
text.
Start
Read Byte
(FD0-FD7)
Read Byte
(FD0-FD7) (1)
Read Byte
(FD0-FD7) (1,2)
Twice
Program/Erase
Operaton Not
Complete, Write
Reset Command
Toggle Bit
= Toggle?
FD5 = 1
?
Toggle Bit
= Toggle?
No
Yes
No
Program/Erase
Operaton
Complete
No
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相關代理商/技術參數 |
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| WEDPNF8M721V-1012BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1012BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1015BM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
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