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CHAPTER 19
PLL FREQUENCY SYNTHESIZER
User’s Manual U12790EJ2V0UD
19.5 PLL Disable Status
The PLL frequency synthesizer can be stopped (PLL disable status) by performing any of the following settings
while the PLL frequency synthesizer is operating.
Setting the value of bit 3 (PLLRF3) of the PLL reference mode register (PLLRF) to 1 to set the PLL disable status
Setting STOP mode using the STOP instruction
Setting the reset using the reset function
The following table shows the operation of each block and the status of each register in the PLL disable status.
Table 19-4. Operation of Each Block and Register Status in PLL Disable Status
Block/Register
Status in PLL Disable Status
VCOL and VCOH pins
Status set in bit 3 (VCOHDMD) and bit 2
(VCOLDMD) of PLLMD
Programmable divider
Division stops
Reference frequency generator
Output stops
Phase comparator
Output stops
EO0 and EO1 pin
High impedance
PLL mode select register
Retains value on execution of write instruction
PLL data register
PLL unlock FF judge register
19.6 Notes on PLL Frequency Synthesizer
Notes on using PLL frequency synthesizer
Because the input pins (VCOL and VCOH pins) of the PLL frequency synthesizer are provided with an AC
amplifier, cut the DC component of the input signal by connecting a capacitor to the input pins in series.
The potential of the selected input pin is intermediate (about 1/2VDD). An unselected input pin becomes the status
set in bit 3 (VCOHDMD) and bit 2 (VCOLDMD) of the PLL mode select register (PLLMD).
For the frequencies that can actually be input and the input amplitude, refer to CHAPTER 25 ELECTRICAL
SPECIFICATIONS.