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CHAPTER 13
SERIAL INTERFACE SIO0
User’s Manual U12790EJ2V0UD
(7) Error detection
In the I2C bus mode, transmit error detection can be performed by the following methods because the serial
bus SDA0 (SDA1) status during transmission is also taken into serial I/O shift register 0 (SIO0) of the
transmitting device.
(a) Comparison of SIO0 data before and after transmission
In this case, a transmit error is judged to have occurred if the two data values are different.
(b) Using the slave address register 0 (SVA0)
Transmit data is set in SIO0 and SVA0 before transmission is performed. After transmission, the COI
bit (match signal from the address comparator) of serial operating mode register 0 (CSIM0) is tested: "1"
indicates normal transmission, and "0" indicates a transmit error.
(8) Communication operation
In the I2C bus mode, the master selects the slave device communicate with from among multiple devices by
outputting address data onto the serial bus.
After the slave address data, the master sends the R/W bit, which indicates the data transfer direction, and
starts serial communication with the selected slave device.
Data communication timing charts are shown in Figures 13-44 and 13-45.
In the transmitting device, serial I/O shift register 0 (SIO0) shifts transmit data to the SO latch in synchronization
with the falling edge of the serial clock (SCL), the SO0 latch outputs the data on an MSB-first basis from the
SDA0 or SDA1 pin to the receiving device.
In the receiving device, the data input from the SDA0 or SDA1 pin is taken into serial I/O shift register 0 (SIO0)
in synchronization with the rising edge of SCL.