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CHAPTER 13
SERIAL INTERFACE SIO0
User’s Manual U12790EJ2V0UD
(f)
Busy signal (BUSY) and ready signal (READY)
The BUSY signal is used to report to the master device that the slave device is not ready for data
transmission/reception.
The READY signal is intended to report to the master device that the slave device is ready for data
transmission/reception.
Figure 13-20. BUSY and READY Signals
In SBI, the slave device notifies the master device of the busy state by setting the SB0 (SB1) line to the
low level.
BUSY signal output follows acknowledge signal output from the master or slave device. It is set/reset
at the falling edge of SCK0. When the BUSY signal is reset, the master device automatically terminates
the output of the SCK0 serial clock.
When the BUSY signal is reset and the READY signal is set, the master device can start the next transfer.
Caution In the SBI mode, SBI outputs the BUSY signal after the BUSY clear instruction has been
executed until the next serial clock falls. If WUP is set to 1 by mistake during this period,
BUSY will not be cleared. Before setting WUP to 1, therefore, clear BUSY, and make sure
that the SB0 (SB1) pin has gone high.
(3) Register setting
The SBI mode is set using serial operating mode register 0 (CSIM0), serial bus interface control register 0
(SBIC0), interrupt timing specification register 0 (SINT0), port mode register 2 (PM2), and port 2 (P2).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets CSIM0 to 00H.
READY
ACK
SCK0
SB0 (SB1)
BUSY
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