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CHAPTER 13
SERIAL INTERFACE SIO0
User’s Manual U12790EJ2V0UD
R/W
CSIM01
Selection of serial interface SIO0 clock
0
Clock input from off-chip to SCK0/SCL/P27 pin
1
Clock specified by bits 0 to 3 of serial interface clock select register 0 (SCL0)
R/W
CSIM CSIM CSIM PM25 P25 PM26 P26 PM27 P27 Operating
Start SI0/SB0/SDA0/ SO0/SB1/SDA1/ SCK0/SCL/P27
04
03
02
mode
bit
P25 pin function
P26 pin function pin function
0
×
3-wire serial I/O mode (refer to 13.4.2 3-wire serial I/O mode operation)
1
0
SBI mode (refer to 13.4.3 SBI mode operation)
11
0
××
0
1
2-wire serial
MSB P25
SB1/SDA1
SCK0/SCL
Note 2 Note 2
I/O (refer to
(CMOS I/O)
(N-ch open-
13.4.4) or I2C
drain I/O)
10
0
××
01
bus mode
SB0/SDA0
P26
Note 2 Note 2
(N-ch open-
(CMOS I/O)
drain I/O)
R/W
WUP
Control of wakeup functionNote 3
0
Interrupt request signal generated with each serial transfer in any mode
1
In I2C bus mode, interrupt request signal is generated when the address data received after start condition
detection (when CMDD = 1) matches the data in slave address register 0.
R
COI
Slave address comparison result flagNote 4
0
Slave address register 0 and serial I/O shift register 0 data do not match
1
Slave address register 0 and serial I/O shift register 0 data match
R/W
CSIE0
Control of serial interface SIO0 operation
0
Operation stopped
1
Operation enabled
Caution
When using SCL, set P27 to 1. If P27 is set to 0, it always outputs a low level.
Notes 1. Bit 6 (COI) is a read-only bit.
2. Can be used freely as a port.
3. When using the wakeup function in the I2C bus mode (WUP = 1), set bit 5 (SIC) of interrupt timing
specification register 0 (SINT0) to 1. Do not execute a write instruction to serial I/O shift register 0 (SIO0)
while WUP = 1.
4. When CSIE0 = 0, COI is 0.
Remark
×:
Don’t care
PM
××: Port mode register
P
××:
Output latch of port
<6>
<5>
4
3210
<7>
Symbol
CSIM0
FF60H
00H
R/WNote 1
Address
After reset
R/W
CSIE0 COI
WUP CSIM04 CSIM03 CSIM02 CSIM01
0