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CHAPTER 18
INTERRUPT FUNCTIONS
User’s Manual U12790EJ2V0UD
Table 18-1. Interrupt Sources (1/6)
(1)
PD178076, 178078 (1/2)
Default
Interrupt Source
Internal/
Vector
Basic
Interrupt Type
PriorityNote 1
External
Table
Configuration
Name
Trigger
Address
TypeNote 2
Non-maskable
–
INTWDT
Overflow of watchdog timer
Internal
0004H
(A)
(when watchdog timer mode 1 is selected)
Maskable
0
INTWDT
Overflow of watchdog timer
(B)
(when interval timer mode is selected)
1
INTP0
Pin input edge detection
External
0006H
(C)
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTP7
0014H
9
INTCSI0
End of transfer by serial interface SIO0
Internal
0016H
(B)
10
INTCSI1
End of transfer by serial interface SIO1
0018H
11
INTCSI3
End of transfer by serial interface SIO3
001AH
12
INTTM50
Generation of match signal of 8-bit
001CH
timer/event counter 50
13
INTTM51
Generation of match signal of 8-bit
001EH
timer/event counter 51
14
INTSER0
Reception error of serial interface UART0
0020H
15
INTSR0
End of reception by serial interface UART0
0022H
16
INTST0
End of transmission by serial interface
0024H
UART0
17
INTBTM0 Generation of coincidence signal of basic
0026H
timer BTM0
18
INTTM00
Generation of signal indicating match
0028H
between 16-bit timer counter 0 (TM0) and
capture/compare register 00 (CR00) (when
CR00 is used as compare register)
Detection of input edge of TI00/P32 pin
External
(D)
(when CR00 is used as capture register)
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or held pending
according to their default priorities. A default priority of 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type correspond to (A) to (E) in Figure 18-1.