
110
User’s Manual U12790EJ2V0UD
CHAPTER 5 CLOCK GENERATOR
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The system clock
oscillator oscillates at frequencies of 6.3 MHzNote. Oscillation can be stopped by executing the STOP instruction or
setting the processor clock control register (PCC).
Note
In addition to the 6.3 MHz crystal resonator, a 4.5 MHz crystal resonator can also be connected to the
PD178078 and 178098A Subseries. When using the system clock at a frequency of 4.5 MHz, set bit 0
(DTSCK0) of the DTS system clock select register (DTSCK) to 1. Set the DTSCK0 flag after power
application and reset by the RESET pin, and before using the basic timer, buzzer output controller (BEEP0),
PLL frequency synthesizer, and frequency counter.
When using the IEBus controller of the
PD178096A, 178098A, and 178F098, however, be sure to use
the 6.3 MHz crystal resonator. At this time, it is not necessary to set the DTSCK0 flag.
The timing of the basic timer, buzzer output controller (BEEP0), PLL frequency synthesizer, and frequency
counter described in 8.3 Operation of Basic Timer, 10.3.1 (1) BEEP frequency select register 0
(BEEPCL0), 19.3 (2) PLL reference mode register (PLLRF), and 20.3 (1) IF counter mode select
register (IFCMD) is not changed.
Figure 5-1. Format of DTS System Clock Select Register (DTSCK)
DTSCK0
System clock selection
0
6.3 MHz
1
4.5 MHz
7
0
6
0
5
0
4
0
3
0
2
0
1
0
DTSCK0
Symbol
DTSCK
Address
FFAAH
After reset
00H
R/W