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TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 2-18. Host-Port Interface Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
Host-Port Interface (HPI)
IPU
DV
DD33
HD0/VLYNQ_SCRUN/
AD18/GP[58]
HD1/VLYNQ_RXD0/
AD16/GP[59]
HD2/VLYNQ_RXD1/
AD17/GP[60]
HD3/VLYNQ_RXD2/
PCBE2/GP[61]
HD4/VLYNQ_RXD3/
PFRAME/GP[62]
HD5/VLYNQ_TXD0/
PIRDY/GP[63]
HD6/VLYNQ_TXD1/
PTRDY/GP[64]
HD7/VLYNQ_TXD2/
PDEVSEL/GP[65]
HD8/VLYNQ_TXD3/
PPERR/GP[66]
HD9/MCOL/
PSTOP/GP[67]
HD10/MCRS/
PSERR/GP[68]
HD11/MTXD3/
PCBE1/GP[69]
HD12/MTXD2/
PPAR/GP[70]
HD13/MTXD1/
AD14/GP[71]
HD14/MTXD0/
AD15/GP[72]
HD15/MTXCLK/
AD12/GP[73]
C8
B9
D7
C9
A8
A9
B7
B8
C7
C8
A6
A7
D6
C7
This pin is multiplexed between HPI, VLYNQ or EMAC, PCI,
and GPIO.
In HPI mode, these pins are host-port data pins HD[15:0]
(
I/O/Z
) and are multiplexed internally with the HPI address
lines.
B6
B7
I/O/Z
IPD
DV
DD33
A5
A6
C6
C6
B5
B6
C5
A5
D5
C5
B4
B4
D4
B5
A4
A4
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is half-word identification input HHWIL
(
I
).
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is control input 1 HCNTL1 (
I
). The state
of HCNTL1 and HCNTL0 determines if address, data, or
control information is being transmitted between an external
host and the DM6437.
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is control input 0 HCNTL0 (
I
). The state
of HCNTL1 and HCNTL0 determines if address, data, or
control information is being transmitted between an external
host and the DM6437.
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is host read or write select input
HR/W(
I
).
This pin is multiplexed between HPI, EMAC, PCI, and GPIO.
In HPI mode, this pin is host data strobe input 2 HDS2 (
I
).
HHWIL/MRXDV/
AD13/GP[74]
IPD
DV
DD33
C4
D3
I/O/Z
HCNTL1/MTXEN/
AD11/GP[75]
IPD
DV
DD33
D3
C4
I/O/Z
HCNTL0/MRXER/
AD10/GP[76]
IPD
DV
DD33
B3
B2
I/O/Z
HR/W/MRXCLK/
AD8/GP[77]
IPD
DV
DD33
A3
A3
I/O/Z
HDS2/MRXD0/
AD9/GP[78]
IPU
DV
DD33
C3
C2
I/O/Z
(1)
(2)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see
Section 3.9.1
,
Pullup/Pulldown Resistors
.
Specifies the operating I/O supply voltage for each signal
(3)
Device Overview
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