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P
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 2-11. EMIFA Terminal Functions (EMIFA Pinout Mode 3, AEM[2:0] = 011) (continued)
SIGNAL
TYPE
(1)
OTHER
(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
CI0(CCD8)/
EM_A[20]/
PINTA/
EM_D[7]/GP[44]
CI1(CCD9)/
EM_A[19]/
PREQ/
EM_D[6]/GP[45]
CI2(CCD10)/
EM_A[18]/
PRST/
EM_D[5]/GP[46]
CI3(CCD11)/
EM_A[17]/
AD31/
EM_D[4]/GP[47]
CI4(CCD12)/
EM_A[16]/
PGNT/
EM_D[3]/GP[48]
CI5(CCD13)/
EM_A[15]/
AD29/
EM_D[2]/GP[49]
CI6(CCD14)/
EM_A[14]/
AD27/
EM_D[1]/GP[50]
CI7(CCD15)/
EM_A[13]/
AD25/
EM_D[0]/GP[51]
IPD
DV
DD33
C12
C15
I/O/Z
IPD
DV
DD33
B12
C14
I/O/Z
IPD
DV
DD33
D11
A14
I/O/Z
IPD
DV
DD33
A11
B14
I/O/Z
This pin is multiplexed between VPFE (CCDC), EMIFA, PCI, and
GPIO.
For EMIFA (AEM[2:0] = 011], these pins are the 8-bit bi-directional
data bus (EM_D[7:0]).
IPD
DV
DD33
C11
B13
I/O/Z
IPD
DV
DD33
B11
C13
I/O/Z
IPD
DV
DD33
A10
A13
I/O/Z
IPD
DV
DD33
B10
A12
I/O/Z
This pin is multiplexed between EMIFA, PCI, and GPIO.
EM_A[12]/PCBE3/
GP[89]
IPD
DV
DD33
D10
B12
I/O/Z
For EMIFA, it is address bit 12 output EM_A[12].
This pin is multiplexed between EMIFA, PCI, and GPIO.
EM_A[11]/AD24/
GP[90]
IPD
DV
DD33
C10
C12
I/O/Z
For EMIFA, it is address bit 11 output EM_A[11].
This pin is multiplexed between EMIFA, PCI, and GPIO.
EM_A[10]/AD23/
GP[91]
IPD
DV
DD33
A9
B11
I/O/Z
For EMIFA, it is address bit 10 output EM_A[10].
This pin is multiplexed between EMIFA, PCI, and GPIO.
EM_A[9]/PIDSEL/
GP[92]
IPD
DV
DD33
D9
C11
I/O/Z
For EMIFA, it is address bit 9 output EM_A[9].
This pin is multiplexed between EMIFA, PCI, and GPIO.
EM_A[8]/AD21/
GP[93]
IPD
DV
DD33
B9
A11
I/O/Z
For EMIFA, it is address bit 8 output EM_A[8].
This pin is multiplexed between EMIFA, PCI, and GPIO.
EM_A[7]/AD22/
GP[94]
IPD
DV
DD33
C9
C10
I/O/Z
For EMIFA, it is address bit 7 output EM_A[7].
This pin is multiplexed between EMIFA, PCI, and GPIO.
EM_A[6]/AD20/
GP[95]
IPD
DV
DD33
D8
B10
I/O/Z
For EMIFA, it is address bit 6 output EM_A[6].
This pin is multiplexed between EMIFA, PCI, and GPIO.
EM_A[5]/AD19/
GP[96]
IPD
DV
DD33
B8
A10
I/O/Z
For EMIFA, it is address bit 5 output EM_A[5].
R0/EM_A[4]/
GP[10]/
(AEAW2/PLLMS2)
This pin is multiplexed between VPBE (VENC), EMIFA, and GPIO.
IPD
DV
DD33
A17
B21
I/O/Z
For EMIFA, it is address bit 4 output EM_A[4].
Device Overview
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