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P
Host Block (27 pins)
(A)(C)
PCI (27)
PCIEN=1
HOSTBK=000
GPIO (27)
PCIEN=0
HOSTBK=000
VLYNQ
(10)
GPIO (17)
VLYNQ
(10)
EMAC (15)
MDIO
(2)
PCIEN=0
HOSTBK=001
PCIEN=0
HOSTBK=010
PCIEN=0
HOSTBK=011
PCIEN=0
HOSTBK=100
HPI (26)
GPIO (1)
EMAC (15)
MDIO
(2)
GPIO (10)
GPIO Block (4 pins)
(C)
PCI
(4)
PCIEN=1
GPIO
(4)
PCIEN=0
UART0 Data Block (2 pins)
GPIO (2)
UR0DBK=0
UART
Data (2)
UR0DBK=1
UART0 Flow Control Block (2 pins)
GPIO (2)
UR0FCBK=00
UART0
FlowCtrl (2)
UR0FCBK=01
PWM0 (1)
GPIO (1)
UR0FCBK=10
Timer1 Block (2 pins)
GPIO (2)
TIM1BK=00
Timer1
(2)
TIM1BK=01
UART1
Data (2)
TIM1BK=10
HECC
(2)
TIM1BK=11
Timer0 Block (2 pins)
(D)(E)
GPIO (2)
TIM0BK=00
Timer0
(2)
TIM0BK=01
McBSP0
CLKS0 (1)
TIM0BK=10
McBSP1
CLKS1 (1)
McBSP0
CLKS0 (1)
TIM0BK=11
Timer0
TINPOL (1)
PWM 1 Block (1 pin)
GPIO
(1)
PWM1BK=0
PWM1
(1)
PWM1BK=1
CLKOUT Block (1 pin)
GPIO
(1)
CKOBK=00
CLKOUT
(1)
CKOBK=01
PWM2
(1)
CKOBK=10
Serial Port Sub-Block 0 (6 pins)
(D)
GPIO (6)
SPBK0=00
McBSP0
(6)
SPBK0=01
McASP0 Receive
and 3 Serializers (6)
SPBK0=10
Serial Port Sub-Block 1 (6 pins)
(E)
GPIO (6)
SPBK1=00
McBSP1
(6)
SPBK1=01
McASP0
Transmit and
1 Serializer (6)
SPBK1=10
McBSP1
Transmit (3)
SPBK1=11
McASP0
SPDIF (3)
EMIFA/VPSS Block (61 pins)
(A)(B)(C)
8-24b
VPBE
Major Config
Option A
8-16b
VPFE
GPIO
8-24b
VPBE
Major Config
Option F
8b
VPFE
GPIO
PCI
8b
VPBE
Major Config
Option B
GPIO
8-16b
VPFE
8b EMIFA
(Async)
Pinout
Mode 1
32KB-16MB
per CE
8-16b
VPBE
Major Config
Option C
GPIO
8b
VPFE
8b EMIFA
(Async)
Pinout
Mode 3
32KB per
CE
8-16b
VPBE
Major Config
Option D
GPIO
8b
VPFE
8b EMIFA
(NAND)
Pinout
Mode 4
8b
VPBE
Major Config
Option E
GPIO
8-16b
VPFE
8b EMIFA
(NAND)
Pinout
Mode 5
8b
VPBE
Major Config
Option G
GPIO
8b
VPFE
8b EMIFA
(NAND)
Pinout
Mode 5
PCI
PCI Data Block (3 pins)
(C)
PCI (3)
Not muxed
AEM=000,
PCIEN=0
AEM=001,
PCIEN=0
AEM=011,
PCIEN=0
AEM=100,
PCIEN=0
AEM=101,
PCIEN=0
AEM=000,
PCIEN=1
AEM=101,
PCIEN=1
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
A.
B.
Default settings for PINMUX0 and PINMUX1 registers are underlined.
EMIFA/VPSS Block: shows the Major Config Options based on the AEM and PCIEN settings. Actual pin functions in
the EMIFA/VPSS Block are further determined by other PINMUX fields.
PCI pins span multiple blocks (Host Block, GPIO Block, EMIFA/VPSS Block, and PCI Data Block). For PCI to be
operational, PCI pins must be selected in all of these Pin Mux Blocks. For the EMIFA/VPSS Block, PCI is only
supported if AEM = 000b or 101b.
McBSP0 pins span multiple blocks (Serial Port Sub-Block0 and Timer0 Block). Serial Port Sub-Block0 contains most
of the pins needed for McBSP0 operation. Timer0 Block contains the optional external clock source input CLKS0.
McBSP1 spans multiple blocks (Serial Port Sub-Block1, Timer0 Block). Serial Port Sub-Block1 contains most of the
pins needed for McBSP1 operation. Timer0 Block contains the optional external clock soruce input CLKS1.
C.
D.
E.
Figure 3-11. Pin Mux Block Selection
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Device Configurations
103