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TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-25. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module
(1)(2)
(see
Figure 6-14
and
Figure 6-15
)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
READS and WRITES
1
t
d(TURNAROUND)
Turn around time
(TA + 1) * E - TBD
(TA + 1) * E + TBD
ns
READS
(RS + RST + RH) *
(RS + RST + RH) * E +
EMIF read cycle time (EW = 0)
ns
E - TBD
TBD
3
t
c(EMRCYCLE)
(RS + RST + RH) *
EMIF read cycle time (EW = 1)
4188 * E + TBD
ns
E - TBD
Output setup time, EM_CS[5:2] low to EM_OE low (SS
= 0)
Output setup time, EM_CS[5:2] low to EM_OE low (SS
= 1)
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 0)
Output hold time, EM_OE high to EM_CS[5:2] high
(SS = 1)
Output setup time, EM_BA[1:0] valid to EM_OE low
Output hold time, EM_OE high to EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to EM_OE low
Output hold time, EM_OE high to EM_A[21:0] invalid
(RS + 1) * E - TBD
(RS + 1) * E + TBD
ns
4
t
su(EMCSL-EMOEL)
TBD
ns
(RH + 1) * E - TBD
(RH + 1) * E + TBD
ns
5
t
h(EMOEH-EMCSH)
TBD
ns
6
7
8
9
t
su(EMBAV-EMOEL)
t
h(EMOEH-EMBAIV)
t
su(EMBAV-EMOEL)
t
h(EMOEH-EMBAIV)
(RS + 1) * E - TBD
(RH + 1) * E - TBD
(RS + 1) * E - TBD
(RH + 1) * E - TBD
(RST + 1) * E -
(RS + 1) * E + TBD
(RH + 1) * E + TBD
(RS + 1) * E + TBD
(RH + 1) * E + TBD
ns
ns
ns
ns
EM_OE active low width (EW = 0)
(RST + 1) * E + TBD
ns
TBD
10
t
w(EMOEL)
(RS + RST + RH) *
EM_OE active low width (EW = 1)
(RST + 4087) * E + TBD
ns
E - TBD
11
t
d(EMWAITH-EMOEH)
Delay time from EM_WAIT deasserted to EM_OE high
4E + TBD
ns
WRITES
(RS + RST + RH) *
(RS + RST + RH) * E +
EMIF write cycle time (EW = 0)
ns
E - TBD
TBD
15
t
c(EMWCYCLE)
(RS + RST + RH) *
EMIF write cycle time (EW = 1)
4188 * E + TBD
ns
E - TBD
Output setup time, EM_CS[5:2] low to EM_WE low
(SS = 0)
Output setup time, EM_CS[5:2] low to EM_WE low
(SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high
(SS = 0)
Output hold time, EM_WE high to EM_CS[5:2] high
(SS = 1)
Output setup time, EM_R/W valid to EM_WE low
Output hold time, EM_WE high to EM_R/W invalid
Output setup time, EM_BA[1:0] valid to EM_WE low
Output hold time, EM_WE high to EM_BA[1:0] invalid
Output setup time, EM_A[21:0] valid to EM_WE low
Output hold time, EM_WE high to EM_A[21:0] invalid
(WS + 1) * E - TBD
(WS + 1) * E + TBD
ns
16
t
su(EMCSL-EMWEL)
TBD
ns
(WH + 1) * E - TBD
(WH + 1) * E + TBD
ns
17
t
h(EMWEH-EMCSH)
TBD
ns
18
19
20
21
22
23
t
su(EMRNW-EMWEL)
t
h(EMWEH-EMRNW)
t
su(EMBAV-EMWEL)
t
h(EMWEH-EMBAIV)
t
su(EMAV-EMWEL)
t
h(EMWEH-EMAIV)
(WS + 1) * E - TBD
(WH + 1) * E - TBD
(WS + 1) * E - TBD
(WH + 1) * E - TBD
(WS + 1) * E - TBD
(WH + 1) * E - TBD
(WS + 1) * E + TBD
(WH + 1) * E + TBD
(WS + 1) * E + TBD
(WH + 1) * E + TBD
(WS + 1) * E + TBD
(WH + 1) * E + TBD
ns
ns
ns
ns
ns
ns
(1)
RS = Read setup, RST = Read STrobe, RH = Read Hold, WS = Write Setup, WST = Write STro`be, WH = Write Hold, TA = Turn
Around, EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous Bank and
Asynchronous Wait Cycle Configuration Registers.
E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 600 MHz, use E =
10
ns.
(2)
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Peripheral Information and Electrical Specifications
209