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TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 2-3. Memory Map Summary
START
ADDRESS
END
SIZE
(Bytes)
C64x+
EDMA PERIPHERAL
MEMORY MAP
VPSS
PCI
ADDRESS
MEMORY MAP
MEMORY MAP
MEMORY MAP
0x0000 0000
0x000F FFFF
1M
Reserved
0x0010 0000
0x0010 FFFF
64K
Boot ROM
0x0011 0000
0x007F FFFF
7M-64K
Reserved
0x0080 0000
0x0081 FFFF
128K
L2 RAM/Cache
(1)
0x0082 0000
0x00E0 7FFF
6048K
Reserved
0x00E0 8000
0x00E0 FFFF
32K
L1P RAM/Cache
(1)
Reserved
Reserved
0x00E1 0000
0x00F0 3FFF
976K
Reserved
0x00F0 4000
0x00F0 FFFF
48K
L1D RAM
0x00F1 0000
0x00F1 7FFF
32K
L1D RAM/Cache
(1)
0x00F1 8000
0x017F FFFF
9120K
Reserved
0x0180 0000
0x01BF FFFF
4M
CFG Space
0x01C0 0000
0x01FF FFFF
4M
CFG Bus Peripherals
CFG Bus Peripherals
CFG Bus Peripherals
0x0200 0000
0x100F FFFF
225M
Reserved
0x1010 0000
0x1010 FFFF
64K
Boot ROM
Reserved
Reserved
0x1011 0000
0x107F FFFF
7M-48K
Reserved
0x1080 0000
0x1081 FFFF
128K
L2 RAM/Cache
(1)
L2 RAM/Cache
(1)
L2 RAM/Cache
(1)
0x1082 0000
0x10E0 7FFF
6048K
Reserved
Reserved
Reserved
0x10E0 8000
0x10E0 FFFF
32K
L1P RAM/Cache
(1)
L1P RAM/Cache
(1)
L1P RAM/Cache
(1)
0x10E1 0000
0x10F0 3FFF
976K
Reserved
Reserved
Reserved
Reserved
0x10F0 4000
0x10F0 FFFF
48K
L1D RAM
L1D RAM
L1D RAM
0x10F1 0000
0x10F1 7FFF
32K
L1D RAM/Cache
(1)
L1D RAM/Cache
(1)
L1D RAM/Cache
(1)
0x10F1 8000
0x10FF FFFF
1M-96K
Reserved
Reserved
Reserved
0x1100 0000
0x1FFF FFFF
240M
Reserved
Reserved
Reserved
0x2000 0000
0x2000 7FFF
32K
DDR2 Control Regs
DDR2 Control Regs
DDR2 Control Regs
0x2000 8000
0x2FFF FFFF
256M-32K
Reserved
Reserved
Reserved
0x3000 0000
0x3FFF FFFF
256M
PCI Data
PCI Data
0x4000 0000
0x41FF FFFF
32M
Reserved
Reserved
0x4200 0000
0x42FF FFFF
16M
EMIFA Data (CS2)
(2)
EMIFA Data (CS2)
(2)
0x4300 0000
0x43FF FFFF
16M
Reserved
Reserved
0x4400 0000
0x44FF FFFF
16M
EMIFA Data (CS3)
(2)
EMIFA Data (CS3)
(2)
0x4500 0000
0x45FF FFFF
16M
Reserved
Reserved
0x4600 0000
0x46FF FFFF
16M
EMIFA Data (CS4)
(2)
EMIFA Data (CS4)
(2)
0x4700 0000
0x47FF FFFF
16M
Reserved
Reserved
0x4800 0000
0x48FF FFFF
16M
EMIFA Data (CS5)
(2)
EMIFA Data (CS5)
(2)
0x4900 0000
0x49FF FFFF
16M
Reserved
Reserved
0x4A00 0000
0x4BFF FFFF
32M
Reserved
Reserved
0x4C00 0000
0x4FFF FFFF
64M
VLYNQ (Remote Data)
VLYNQ (Remote Data)
0x5000 0000
0x7FFF FFFF
768M
Reserved
Reserved
0x8000 0000
0x8FFF FFFF
256M
DDR2 Memory Controller
DDR2 Memory Controller
DDR2 Memory Controller
DDR2 Memory Controller
0x9000 0000
0xFFFF FFFF
1792M
Reserved
Reserved
Reserved
Reserved
(1)
For all boot modes that default to DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,
BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2, L1P, and L1D) so that upon exit from the
bootloader code, all C64x+ memories are configured as all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and
L1DCFG.L1DMODE = 0h). If cache use is required, the application code must explicitly enable the cache. For more information on boot
modes, see
Section 3.4.1
,
Boot Modes
. For more information on the bootloader, see the
Using the TMS320DM643x Bootloader
Application Report (literature number
SPRAAG0
). For the EMIFA ROM Direct Boot (BOOTMODE[3:0] = 0100, FASTBOOT = 0), the
bootloader is not executed—that is, L2 RAM/Cache defaults to all RAM (L2CFG.L2MODE = 0h); L1P RAM/Cache defaults to all cache
(L1PCFG.L1PMODE = 7h); and L1D RAM/Cache defaults to all cache (L1DCFG.L1DMODE = 7h).
The EMIFA CS0 and CS1 are
not
functionally supported on the DM6437 device, and therefore, are
not
pinned out.
(2)
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Device Overview
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