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TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
Table 6-57. Switching Characteristics for Host-Port Interface Cycles
(1)(2)(3)
(see
Figure 6-32
through
Figure 6-35
)
-400
-500
-600
NO.
PARAMETER
UNIT
MIN
MAX
For HPI Write, HRDY can go high (
not
ready
) for these HPI Write conditions;
otherwise, HRDY stays low (
ready
):
Case 1
: Back-to-back HPIA writes (can
be either first or second half-word)
Case 2
: HPIA write following a
PREFETCH command (can be either
first or second half-word)
Case 3
: HPID write when FIFO is full
or flushing (can be either first or
second half-word)
Case 4
: HPIA write and Write FIFO not
empty
For HPI Read, HRDY can go high (
not
ready
) for these HPI Read conditions:
Case 1
: HPID read (with
auto-increment) and data not in Read
FIFO (can only happen to first
half-word of HPID access)
Case 2
: First half-word access of HPID
Read without auto-increment
For HPI Read, HRDY stays low (
ready
)
for these HPI Read conditions:
Case 1
: HPID read with auto-increment
and data is already in Read FIFO
(applies to either half-word of HPID
access)
Case 2
: HPID read without
auto-increment and data is already in
Read FIFO (always applies to second
half-word of HPID access)
Case 3
: HPIC or HPIA read (applies to
either half-word access)
Delay time, HSTROBE low to
HRDY valid
5
t
d(HSTBL-HRDYV)
12
ns
6
7
8
t
en(HSTBL-HD)
t
d(HRDYL-HDV)
t
oh(HSTBH-HDV)
t
dis(HSTBH-HDV)
Enable time, HD driven from HSTROBE low
Delay time, HRDY low to HD valid
Output hold time, HD valid after HSTROBE high
Disable time, HD high-impedance from HSTROBE high
2
ns
ns
ns
ns
0
1.5
14
12
For HPI Read. Applies to conditions
where data is already residing in
HPID/FIFO:
Case 1
: HPIC or HPIA read
Case 2
: First half-word of HPID read
with auto-increment and data is
already in Read FIFO
Case 3
: Second half-word of HPID
read with or without auto-increment
For HPI Write, HRDY can go high (
not
ready
) for these HPI Write conditions;
otherwise, HRDY stays low (
ready
):
Case 1
: HPID write when Write FIFO is
full (can happen to either half-word)
Case 2
: HPIA write (can happen to
either half-word)
Case 3
: HPID write without
auto-increment (only happens to
second half-word)
Delay time, HSTROBE low to
HD valid
15
t
d(HSTBL-HDV)
15
ns
Delay time, HSTROBE high to
HRDY valid
18
t
d(HSTBH-HRDYV)
12
ns
(1)
(2)
(3)
M = SYSCLK3 period = (CPU clock frequency)/6 in ns. For example, when running parts at 600 MHz, use M = 10 ns.
TBD
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).
Peripheral Information and Electrical Specifications
246
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