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6.8 Interrupts
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in
Table 6-21
. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts.
Table 6-22
summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP
interrupt controller, see the
TMS320DM643x DMP DSP Subsystem
Reference Guide (literature number
SPRU978
).
Table 6-21. DM6437 DSP System Event Mapping
DSP
DSP
SYSTEM
EVENT
NUMBER
SYSTEM
EVENT
NUMBER
ACRONYM
SOURCE
ACRONYM
SOURCE
0
EVT0
C64x+ Int Ctl 0
64
GPIO0
GPIO
1
EVT1
C64x+ Int Ctl 1
65
GPIO1
GPIO
2
EVT2
C64x+ Int Ctl 2
66
GPIO2
GPIO
3
EVT3
C64x+ Int Ctl 3
67
GPIO3
GPIO
4
TINTL0
Timer 0 – TINT12
68
GPIO4
GPIO
5
TINTH0
Timer 0 – TINT34
69
GPIO5
GPIO
6
TINTL1
Timer 1 – TINT12
70
GPIO6
GPIO
7
TINTH1
Timer 1 – TINT34
71
GPIO7
GPIO
8
WDINT
Timer 2 – TINT12
72
GPIOBNK0
GPIO
9
EMU_DTDMA
C64x+ EMC
73
GPIOBNK1
GPIO
10
Reserved
74
GPIOBNK2
GPIO
11
EMU_RTDXRX
C64x+ RTDX
75
GPIOBNK3
GPIO
12
EMU_RTDXTX
C64x+ RTDX
76
GPIOBNK4
GPIO
13
IDMAINT0
C64x+ EMC 0
77
GPIOBNK5
GPIO
14
IDMAINT1
C64x+ EMC 1
78
GPIOBNK6
GPIO
15
Reserved
79
Reserved
16
Reserved
80
PWM0
PWM0
17
Reserved
81
PWM1
PWM1
18
Reserved
82
PWM2
PWM2
19
Reserved
83
IICINT0
I2C
20
Reserved
84
UARTINT0
UART0
21
Reserved
85
UARTINT1
UART1
22
Reserved
86
Reserved
23
Reserved
87
Reserved
24
VDINT0
VPSS – CCDC 0
88
Reserved
25
VDINT1
VPSS – CCDC 1
89
Reserved
26
VDINT2
VPSS – CCDC 2
90
Reserved
27
HISTINT
VPSS – Histogram
91
Reserved
28
H3AINT
VPSS – AE/AWB/AF
92
Reserved
29
PRVUINT
VPSS – Previewer
93
Reserved
30
RSZINT
VPSS – Resizer
94
Reserved
31
Reserved
95
Reserved
VENCINT
VPSS – VPBE (VENC)
INTERR
C64x+ Interrupt Controller Dropped CPU
Interrupt Event
32
96
33
Reserved
97
EMC_IDMAERR
C64x+ EMC Invalid IDMA Parameters
34
EDMA3CC_GINT
EDMACC Global Interupt
98
Reserved
35
EDMA3CC_INT0
EDMACC Interrupt Region 0
99
Reserved
36
EDMA3CC_INT1
EDMACC Interrupt Region 1
100
Reserved
37
EDMA3CC_ERRINT
EDMA CC Error
101
Reserved
38
EDMA3TC_ERRINT0
EDMA TC0 Error
102
Reserved
39
EDMA3TC_ERRINT1
EDMA TC1 Error
103
Reserved
40
EDMA3TC_ERRINT2
EDMA TC2 Error
104
Reserved
41
PSCINT
PSC ALLINT
105
Reserved
42
Reserved
106
Reserved
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Peripheral Information and Electrical Specifications
203