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TMS320DM6437 Digital Media Processor
1.1 Features
High-Performance Digital Media Processor
(DM6437)
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2.5-, 2.-, 1.67-ns Instruction Cycle Time
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400-, 500-, 600-MHz C64x+ Clock Rate
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Eight 32-Bit C64x+ Instructions/Cycle
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3200, 4000, 4800 MIPS
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Fully Software-Compatible With C64x
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Commercial and Extended Temperature
Ranges
VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+ DSP Core
–
Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
–
Load-Store Architecture With Non-Aligned
Support
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64 32-Bit General-Purpose Registers
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Instruction Packing Reduces Code Size
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All Instructions Conditional
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Additional C64x+ Enhancements
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
Hardware Support for Modulo Loop
Auto-Focus Module Operation
C64x+ Instruction Set Features
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Byte-Addressable (8-/16-/32-/64-Bit Data)
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8-Bit Overflow Protection
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Bit-Field Extract, Set, Clear
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Normalization, Saturation, Bit-Counting
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VelociTI.2 Increased Orthogonality
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C64x+ Extensions
Compact 16-bit Instructions
Additional Instructions to Support
Complex Multiplies
C64x+ L1/L2 Memory Architecture
–
256K-Bit (32K-Byte) L1P Program
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
RAM/Cache [Flexible Allocation]
640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
Supports Little Endian Mode Only
Video Processing Subsystem (VPSS)
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Front End Provides:
CCD and CMOS Imager Interface
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
Preview Engine for Real-Time Image
Processing
Glueless Interface to Common Video
Decoders
Histogram Module
Auto-Exposure, Auto-White Balance and
Auto-Focus Module
Resize Engine
Resize Images From 1/4x to 4x
Separate Horizontal/Vertical Control
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Back End Provides:
Hardware On-Screen Display (OSD)
Four 54-MHz DACs for a Combination of
Composite NTSC/PAL Video
Luma/Chroma Separate Video
(S-video)
Component (YPbPr or RGB) Video
(Progressive)
Digital Output
8-/16-bit YUV or up to 24-Bit RGB
HD Resolution
Up to 2 Video Windows
External Memory Interfaces (EMIFs)
–
32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
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Asynchronous 8-Bit Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
Flash Memory Interfaces
NOR (8-Bit-Wide Data)
NAND (8-Bit-Wide Data)
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
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