參數(shù)資料
型號: TMS320C6713BGDPA200
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 浮點數(shù)字信號處理器
文件頁數(shù): 93/150頁
文件大?。?/td> 2039K
代理商: TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
93
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers
may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive
TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the
low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins
configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see
the terminal functions section of this data sheet.
EMIF device speed
The maximum EMIF speed on the C6713/13B device is 100 MHz. TI recommends utilizing I/O buffer information
specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given
board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the
Using
IBIS Models for Timing Analysis
application report (literature number SPRA839).
For ease of design evaluation, Table 46 contains IBIS simulation results showing the maximum EMIF-SDRAM
interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be
performed to verify that all AC timings are met for the specified board layout. Other configurations are also
possible, but again, timing analysis must be done to verify proper AC timings.
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
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