參數(shù)資料
型號： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 137/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
137
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0
(see Figure 59)
NO.
PARAMETER
13PYPA
167
13PYP
200
13GDPA
200
13GDP
225
13BPYPA
167
13BPYP
200
13BGDPA
200
13BGDP
225
13BGDP
300
UNIT
MASTER
§
MIN
SLAVE
MIN
MASTER
§
MIN
SLAVE
MIN
MAX
MAX
MAX
MAX
1
t
h(CKXL-FXL)
Hold time, FSX low
after CLKX low
T
2
T + 3
T
2
T + 3
ns
2
t
d(FXL-CKXH)
Delay time, FSX low to
CLKX high
#
L
2
L + 3
L
2
L + 3
ns
3
t
d(CKXH-DXV)
Delay time, CLKX high to
DX valid
3
4
6P + 2
10P + 17
3
4
6P + 2
10P + 17
ns
6
t
dis(CKXL-DXHZ)
Disable time, DX high
impedance following last
data bit from CLKX low
L
4
L + 3
L
2
L + 3
ns
7
t
dis(FXH-DXHZ)
Disable time, DX high
impedance following last
data bit from FSX high
2P + 1.5
6P + 17
2P + 3
6P + 17
ns
8
t
d(FXL-DXV)
Delay time, FSX low to
DX valid
4P + 2
8P + 17
4P + 2
8P + 17
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§
S =
Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T =
CLKX period = (1 + CLKGDV) * S
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
5
4
3
8
7
6
2
1
CLKX
FSX
DX
DR
Figure 59. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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參數(shù)描述
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TMS320C6713BPYP225 制造商:Texas Instruments 功能描述:
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