參數(shù)資料
型號： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 53/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
PIN NO.
PYP
TYPE
IPD/
IPU
DESCRIPTION
GDP
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) (CONTINUED)
M1
I/O/Z
IPD
McBSP1 receive clock (
I/O/Z
) [default] or McASP0 TX/RX data pin 6 (I/O/Z).
L2
I/O/Z
IPU
McBSP1 transmit data (
O/Z
) [default] or McASP0 TX/RX data pin 5 (I/O/Z).
F1
I/O/Z
IPD
Timer 1 output (
O
) [default] or McASP0 TX/RX data pin 4 (I/O/Z).
G2
I/O/Z
IPD
Timer 0 input (
I
) [default] or McASP0 TX/RX data pin 3 (I/O/Z).
G1
I/O/Z
IPD
Timer 0 output (
O
) [default] or McASP0 TX/RX data pin 2 (I/O/Z).
H2
I/O/Z
IPU
McBSP0 transmit data (
O/Z
) [default] or McASP0 TX/RX data pin 1 (I/O/Z).
J1
I/O/Z
IPU
McBSP0 receive data (
I
) [default] or McASP0 TX/RX data pin 0 (I/O/Z).
TIMER 1
F1
O
IPD
Timer 1 output (
O
) [default] or McASP0 TX/RX data pin 4 (I/O/Z).
Timer 1 input (
I
) [default] or McBSP0 transmit high-frequency master clock
(I/O/Z).
CLKR1/AXR0[6]
DX1/AXR0[5]
TOUT1/AXR0[4]
TINP0/AXR0[3]
TOUT0/AXR0[2]
DX0/AXR0[1]
DR0/AXR0[0]
36
32
13
17
18
20
27
TOUT1/AXR0[4]
13
TINP1/AHCLKX0
12
F2
I
IPD
TIMER0
Timer 0 output (
O
) [default] or McASP0 TX/RX data pin 2 (I/O/Z).
Timer 0 input (
I
) [default] or McASP0 TX/RX data pin 3 (I/O/Z).
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
McBSP1 external clock source (as opposed to internal) (
I
) [default] or I2C1
clock (I/O/Z).
This pin does not have an internal pullup or pulldown. When this pin is used as a
McBSP pin, this pin should either be driven externally at all times or be pulled up
with a 10-k
resistor to a valid logic level. Because it is common for some ICs to
3-state their outputs at times, a 10-k
pullup resistor may be desirable even
when an external device is driving the pin.
TOUT0/AXR0[2]
TINP0/AXR0[3]
18
17
G1
G2
O
I
IPD
IPD
CLKS1/SCL1
8
E1
I
—
CLKR1/AXR0[6]
CLKX1/AMUTE0
36
33
M1
L3
I/O/Z
I/O/Z
IPD
IPD
McBSP1 receive clock (
I/O/Z
) [default] or McASP0 TX/RX data pin 6 (I/O/Z).
McBSP1 transmit clock (
I/O/Z
) [default] or McASP0 mute output (O/Z).
McBSP1 receive data (
I
) [default] or I2C1 data (I/O/Z).
This pin does not have an internal pullup or pulldown. When this pin is used as a
McBSP pin, this pin should either be driven externally at all times or be pulled up
with a 10-k
resistor to a valid logic level. Because it is common for some ICs to
3-state their outputs at times, a 10-k
pullup resistor may be desirable even
when an external device is driving the pin.
DR1/SDA1
37
M2
I
—
DX1/AXR0[5]
32
L2
O/Z
IPU
McBSP1 transmit data (
O/Z
) [default] or McASP0 TX/RX data pin 5 (I/O/Z).
McBSP1 receive frame sync (
I/O/Z
) [default] or McASP0 TX/RX data pin 7
(I/O/Z).
FSR1/AXR0[7]
38
M3
I/O/Z
IPD
FSX1
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k
resistor (approximate) for the IPD or 18-k
resistor
(approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k
and 2.0 k
, respectively, should be used to pull a signal
to the opposite supply rail.]
31
L1
I/O/Z
IPD
McBSP1 transmit frame sync
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