參數(shù)資料
型號(hào)： TMS320C6713BGDPA200
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FLOATING-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 浮點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 54/150頁
文件大?。?/td> 2039K
代理商： TMS320C6713BGDPA200
TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
PIN NO.
PYP
TYPE
IPD/
IPU
DESCRIPTION
GDP
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
McBSP0 external clock source (as opposed to internal) (
I
) [default] or McASP0
receive high-frequency master clock (I/O/Z).
CLKS0/AHCLKR0
28
K3
I
IPD
CLKR0/ACLKR0
CLKX0/ACLKX0
DR0/AXR0[0]
DX0/AXR0[1]
19
16
27
20
H3
G3
J1
H2
I/O/Z
I/O/Z
I
O/Z
IPD
IPD
IPU
IPU
McBSP0 receive clock (
I/O/Z
) [default] or McASP0 receive bit clock (I/O/Z).
McBSP0 transmit clock (
I/O/Z
) [default] or McASP0 transmit bit clock (I/O/Z).
McBSP0 receive data (
I
) [default] or McASP0 TX/RX data pin 0 (I/O/Z).
McBSP0 transmit data (
O/Z
) [default] or McASP0 TX/RX data pin 1 (I/O/Z).
McBSP0 receive frame sync (
I/O/Z
) [default] or McASP0 receive frame sync or
left/right clock (LRCLK) (I/O/Z).
FSR0/AFSR0
24
J3
I/O/Z
IPD
FSX0/AFSX0
21
H1
I/O/Z
IPD
McBSP0 transmit frame sync (
I/O/Z
) [default] or McASP0 transmit frame sync or
left/right clock (LRCLK) (I/O/Z).
INTER-INTEGRATED CIRCUIT 1 (I2C1)
McBSP1 external clock source (as opposed to internal) (
I
) [default] or I2C1 clock
(I/O/Z).
This pin
must
be externally pulled up. When this pin is used as an I2C pin, the
value of the pullup resistor is dependent on the number of devices connected to
the I2C bus. For more details, see the
Philips I
2
C Specification Revision 2.1
(January 2000).
McBSP1 receive data (
I
) [default] or I2C1 data (I/O/Z).
This pin
must
be externally pulled up. When this pin is used as an I2C pin, the
value of the pullup resistor is dependent on the number of devices connected to
the I2C bus. For more details, see the
Philips I
2
C Specification Revision 2.1
(January 2000).
CLKS1/SCL1
8
E1
I/O/Z
—
DR1/SDA1
37
M2
I/O/Z
—
INTER-INTEGRATED CIRCUIT 0 (I2C0)
I2C0 clock.
This pin
must
be externally pulled up. The value of the pullup resistor on this pin
is dependent on the number of devices connected to the I2C bus. For more
details, see the
Philips I
2
C Specification Revision 2.1
(January 2000).
I2C0 data.
This pin
must
be externally pulled up. The value of the pullup resistor on this pin
is dependent on the number of devices connected to the I2C bus. For more
details, see
the Philips I
2
C Specification Revision 2.1
(January 2000).
SCL0
41
N1
I/O/Z
—
SDA0
42
N2
I/O/Z
—
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. [These IPD/IPU signal pins feature a 13-k
resistor (approximate) for the IPD or 18-k
resistor
(approximate) for the IPU. An external pullup or pulldown resistor no greater than 4.4 k
and 2.0 k
, respectively, should be used to pull a signal
to the opposite supply rail.]
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