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TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I
DECEMBER 2001
REVISED MAY 2004
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
DEVICE CONFIGURATIONS (CONTINUED)
peripheral selection/device configurations via the DEVCFG control register
The device configuration register (DEVCFG) allows the user to control the pin availability of the McBSP0,
McBSP1, McASP0, I2C1, and Timer peripherals. The DEVCFG register also offers the user control of the EMIF
input clock source and the timer output pins. For more detailed information on the DEVCFG register control bits,
see Table 20 and Table 21.
Table 20. Device Configuration Register (DEVCFG) [Address location: 0x019C0200
0x019C02FF]
31
16
Reserved
RW-0
15
5
4
3
2
1
0
Reserved
EKSRC
TOUT1SEL
TOUT0SEL
MCBSP0DIS
MCBSP1DIS
RW-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Legend:
R/W = Read/Write; -n = value after reset
Do not
write non-zero values to these bit locations.
Table 21. Device Configuration (DEVCFG) Register Selection Bit Descriptions
BIT #
31:5
NAME
Reserved
DESCRIPTION
Reserved.
Do not
write non-zero values to these bit locations.
EMIF input clock source bit.
Determines which clock signal is used as the EMIF input clock.
0
=
SYSCLK3 (from the clock generator) is the EMIF input clock source (default)
1
=
ECLKIN external pin is the EMIF input clock source
Timer 1 output (TOUT1) pin function select bit.
Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral
selection bits in the DEVCFG register.
0
=
The pin functions as a Timer 1 output (TOUT1) pin (default)
1
=
The pin functions as the McASP0 transmit/receive data pin 4 (AXR0[4]).
The Timer 1 module is still active.
Timer 0 output (TOUT0) pin function select bit.
Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral
selection bits in the DEVCFG register.
0
=
The pin functions as a Timer 0 output (TOUT0) pin (default)
1
=
The pin functions as the McASP0 transmit/receive data pin 2 (AXR0[2]).
The Timer 0 module is still active.
Multichannel Buffered Serial Port 0 (McBSP0) disable bit.
Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled.
0
=
McBSP0 peripheral pins are enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0,
ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default).
[If the McASP0 data pins are available, the McASP0 peripheral is functional for DIT
mode only.]
1
=
McBSP0 peripheral pins are disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0,
ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled.
4
EKSRC
3
TOUT1SEL
2
TOUT0SEL
1
MCBSP0DIS
0
MCBSP1DIS
Multichannel Buffered Serial Port 1 (McBSP1) disable bit.
Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled.
0
=
McBSP1 peripheral pins are enabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0
peripheral pins (AXR0[7:5] and AMUTE0) are disabled (default)
1
=
McBSP1 peripheral pins are disabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0
peripheral pins (AXR0[7:5] and AMUTE0) are enabled.