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參數(shù)資料
| 型號(hào)： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 90/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
86
Lucent Technologies Inc.
Questions and Answers
(continued)
U-Interface
(continued)
Q18:
Please clarify the meaning of ANSI Standard
T1.601, Section 7.4.2, Jitter Requirement #3.
A18:
The intent of this requirement is to ensure that
after a deactivation and subsequent activation
attempt (warm start), the phase of the receive
and transmit signals at the NT will be within the
specified limits relative to what they were prior to
deactivation. This is needed so that the LT, upon
a warm-start attempt, can make an accurate
assumption about the phase of the incoming NT
signal with respect to its transmit signal. Note that
the T7256 meets this requirement by design
because the NT phase offset from transmit to
receive is always fixed.
Q19:
I need a way to generate a scrambled 2B1Q data
stream from the T7256 for test purposes (e.g.,
ANSI T1.601 Section 5.3.2.2, Total Power and
Section 7.2, Longitudinal Output Voltage). How
can I do this
A19:
A scrambled 2B1Q data stream (the “SN1” signal
described in ANSI T1.601 Table 5) can be gener-
ated by pulling ILOSS (pin 6) low on the T7256.
Q20:
We are trying to do a return loss measurement on
the U-interface of the T7256 per ANSI T1.601
Section 7.1. We are using a circuit similar to the
one you recommend in the data sheet. We have
observed the following. When the chip is in FULL
RESET mode (powered on but no activity on the
U- or S/T-interfaces), the return loss is very low,
i.e., the termination impedance appears to be
very large relative to 135
and falls outside the
boundaries of Figure 19 of ANSI T1.601. How-
ever, if we inject a 10 kHz tone before making a
measurement, the return loss falls within the tem-
plate. Why is it necessary to inject the 10 kHz
tone in order to get this test to pass Shouldn’t a
135
impedance be presented to the network
regardless of the state of the T7256 once it is
powered on
A20:
The return loss is only relevant when the trans-
mitter section is powered on. When the transmit-
ter is powered, it presents a low-impedance
output to the U-interface. The transmitter must be
held in this low-impedance state when the return
loss
and
longitudinal balance tests are per-
formed. This can be accomplished by pulling
RESET low (pin 43). With the RESET pin held
low, the transmitter is held in a low-impedance
state where each of its differential outputs drives
DV. In this state, it is prevented from transmitting
any 2BIQ data and won’t respond to any incom-
ing wakeup tones. This is different than the ANSI-
defined FULL RESET state that the chip enters
after power-on or deactivation. In FULL RESET,
the transmitter is powered down and in a high-
impedance state, with only the tone detector
powered on and looking for a far-end wakeup
tone. The transmitter powers down when in FULL
RESET state to save power and maximize the
tone detector sensitivity. The reason that the chip
behaves as it does in your tests is that your test
begins with the transmitter in its FULL RESET
state, causing the return loss to be very low. If a
10 kHz signal is applied, the tone detector
senses the applied signal and triggers. This
causes the transmitter to enter its low-impedance
state, where it will remain until the T7256 start-up
state machine times out (typically within 1.5 sec-
onds, depending on the signal from the far end).
Q21:
What are the average cold start and warm start
times
A21:
Lab measurements have shown the average cold
start time to be about 3.3 s—4.2 s over all loop
lengths, and the average warm-start time to be
around 125 ms—190 ms over all loop lengths.
Q22:
What is the U-interface’s response time to an
incoming wakeup tone from the LT
A22:
Response time is about 1 ms.
Q23:
What is the minimum time for a U-interface
reframe after a momentary (<480 ms) loss of syn-
chronization
A23:
Five superframes (60 ms).
Q24:
Where is the U-interface loopback 2 (i.e., eoc
2B+D loopback) performed in the T7256
A24:
It is performed just inside the chip at the S/T-inter-
face. The S/T receiver is disconnected internally
from the chip pins, and the S/T transmit signal is
looped back to the receiver inputs so the S/T sec-
tion synchronizes to its own signal. This ensures
that as much of the data path as possible is being
tested during the 2B+D loopback.
Q25:
Are the embedded operations channel (EOC) ini-
tiated B1 and B2 channel loopbacks transparent
A25:
Yes, the B1 and B2 channel loopbacks are trans-
parent, as is the 2B+D loopback.
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