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參數(shù)資料
| 型號： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 38/116頁 |
| 文件大小： | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
34
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 19. U-Interface Interrupt Register (Address 13h)
These bits are cleared during RESET.
Reg
UIR0
R/W
R
Bit 7
—
Bit 6
—
Bit 5
TSFINT
Bit 4
RSFINT
Bit 3
OUSC
Bit 2
BERR
Bit 1
ACTSC
Bit 0
EOCSC
Register
UIR0
Bit
0
Symbol
EOCSC
Name/Description
eoc State Change on U-Interface.
Activates (set to 1) when the re-
ceived eoc message changes state. Bit is cleared on read. See eoc
State Machine Description section for details.
0—No change in eoc state.
1—eoc state change.
Activation/Deactivation State Change on U-Interface.
Activates (set
to 1) during changes in the status bits monitoring U-interface activation
and deactivation (ACTR and XACT, register CFR1, bits 0 and 1). Bit
cleared on read.
0—No activation/deactivation activity.
1—Change in state of activation/deactivation bits.
Block Error on U-Interface.
Activates (set to 1) when received signal
contains either a near-end (NEBE = 0) or a far-end (FEBE = 0) block er-
ror. Bit cleared on read.
0—No block errors.
1—Block error.
Other U-Interface State Change.
Activates (set to 1) when any of the
following bits change state: OOF, UOA, AIB, and Rx, y (all reserved U-
interface status bits). Bit cleared on read.
0—No state change.
1—State change.
Receive Superframe Interrupt.
Activates (set to 1) when the receive
superframe boundary occurs. Bit cleared on read.
0 to 1—First 2B+D data of the receive U superframe.
Transmit Superframe Interrupt.
Activates (set to 1) when the transmit
superframe boundary occurs. Bit cleared on read.
0 to 1—First 2B+D data of the transmit U superframe.
UIR0
1
ACTSC
UIR0
2
BERR
UIR0
3
OUSC
UIR0
4
RSFINT
UIR0
5
TSFINT
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