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參數(shù)資料
| 型號： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 53/116頁 |
| 文件大小： | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
49
S/T-Interface Multiframing Controller
Description
If an external microprocessor is available, the T7256
can provide the capability of supporting multiframing as
defined in ITU-T I.430 Section 6.3.3 and ANSI T1.605
Section 7.3.3. Multiframing provides layer-1 signaling
capability between the TEs and the NT in both direc-
tions through the use of extra channels referred to as
the S channel for the NT-to-TE direction and the Q
channel for the TE-to-NT direction (see Figure 8 in this
data sheet for the location of the S and Q bits in the NT
and TE frames). This signaling capability is similar to
the eoc channel between the LT and NT on the U-inter-
face. The S and Q channels exist only between the TE
and NT, and there is no requirement that the NT trans-
fers this information to the U-interface.
The requirement for multiframing capability is treated
somewhat differently in ANSI T1.605, ITU-T I.430, and
ETSI ETS 300 012. The ANSI standard states that the
use of the S- and Q-channels is optional (Section
7.3.3). NTs that do not support these channels are not
required to encode the FA and M bits as required for
multiframing. TEs that do not support these channels
still must provide for identification of the Q-bit positions
and, if identified, must set each Q bit to a binary one.
ANSI defines a set of Q-channel messages, and
divides the S channel into five subchannels, defining
messages for S subchannels 1 and 2 (see T1.605
Tables 8 and 9).
ITU-T I.430 contains similar requirements for the S and
Q channels as T1.605, with the following exceptions:
1. There is no "far-end code violation" message for S
subchannel 1 (see ITU-T I.430, Table 9).
2. S subchannel 2 is not defined.
ETSI ETS 300 012 deviates slightly from ITU-T I.430. It
states that the NT1 will not provide multiframing, and
therefore the FA bit from NT-to-TE must be set to zero
(Table A.1, subclause A.6.3.3). An NT2, however, may
optionally provide multiframing in accordance with ITU-
T I.430. In either case, the TEs must provide for identifi-
cation of the Q-bit positions.
The multiframing mechanism in the T7256 is controlled
by the microprocessor. Normally, multiframing is dis-
abled (the NT transmits all zeros in the FA and M bit
positions and all ones in the S bit positions). To enable
multiframing, set MULTIF = 0 in bit 5 of register GR0.
Note that multiframing should only be enabled after the
TE interface is fully active (i.e., transmitting INFO3). In
order to guarantee this, the controller should implement
the following procedure:
1. Initialize MULTIF = 1 (this is the default on pow-
erup).
2. Monitor ACTR (register CFR1, bit 0) with the micro-
processor to detect when the system has activated
and has received INFO3. ACTR reflects the state of
the U-interface act bit from the LT, and is sent by the
LT in response to a reception of the act bit from the
NT. The NT sets act = 1 only after receiving INFO3
on the S/T-interface; so waiting for ACTR = 1
ensures that INFO3 is being received.
The monitoring of the ACTR bit can be interrupt-
driven using the ACTSC bit in interrupt register
UIR0.
3. When ACTR = 1 is detected, set MULTIF = 0 to
enable multiframing.
4. Monitor for a change from XACT = 1 to XACT = 0.
This can also be interrupt-driven using the ACTSC
bit in interrupt register UIR0.
5. When XACT = 0 is detected, this indicates that the
system has deactivated.
At this point, go back to step #1 and repeat the proce-
dure.
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