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參數(shù)資料
| 型號： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 57/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
53
Application Briefs
(continued)
T7256 Reference Circuit
(continued)
Power Status Leads
ANSI T1.601 Section 8.2.4 defines U-interface NT
power status bits ps1 and ps2. These bits are transmit-
ted across the U-Interface via the U maintenance chan-
nel. On the T7256, these bits are controlled by pins 8
and 9 (PS2E and PS1E). When the TDM highway is
used (NT1+ or TA modes), the ps1/ps2 bits are con-
trolled by internal registers that are written by an exter-
nal microprocessor. An NT1 typically has circuitry that
monitors the status of the power supply and sets ps1
and ps2 accordingly. In general, power status monitor-
ing circuitry is dependent on various system parame-
ters and requirements, and must be designed based on
the specific application’s requirements. For this reason,
there is no power status monitoring circuitry shown in
this design. Instead, pull-ups R1 and R2 in Figure 20
are provided to force a default indication of primary and
secondary power good status.
Fixed/Adaptive Timing Control
As detailed in Table 1, pin 7 of the T7256 controls
whether the S/T-interface will use fixed or adaptive tim-
ing recovery. When there is no connection to pin 7, an
internal 100K pull-up holds the pin high, which causes
the chip to default to adaptive timing recovery. JMP1 is
provided (see Figure 20) to change the timing recovery
mode to fixed timing by pulling pin 7 down through a
5.1 k
resistor.
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