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參數(shù)資料
| 型號(hào)： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁數(shù)： | 76/116頁 |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
72
Lucent Technologies Inc.
Application Briefs
(continued)
Available Tools for Evaluation of the T7256
(continued)
Resetting SCNT1
The SPEC_V2 board has a push-button RESET switch
(S1) that may be used to RESET the 8751 microcon-
troller on the SPEC_V2. Asserting RESET will restart
the SPEC_V2 firmware. Upon power-on or RESET, the
SPEC_V2 displays the opening screen on the terminal,
and it appears as follows:
Lucent Technologies
SPEC_V2 Control Software, V 1.0, 6/2/96
(type "help" (lower case) for a list of commands)
At this point, any of the commands in Table 33 may be
entered.
If the current test mode is either single pulse or eye
pattern mode, the microcontroller will reset the SCNT1
when exiting that mode. This is necessary because the
only way to exit these test modes is by resetting
SCNT1 or cycling the power. The reset is accomplished
by pulling the SCNT1 RESET line (pin 43) low. Note
that this requires that any device on the UUT that
drives that RESET pin must have an open-drain or 3-
statable type of output. If RESET cannot be pulled low
due to device contention on the UUT, the UUT must be
powered down to get the SCNT1 out of test mode.
Notes on Single Pulse Mode
Note that, when a single pulse is output on the U-inter-
face, the following will be observed: approximately
25 ms after the rising edge of a single positive pulse, a
small positive glitch will occur. This is more pronounced
on +1 pulses than on +3 pulses, where it is hardly
detectable. The cause of the glitch is well understood
and was thoroughly investigated during the chip devel-
opment to ensure that it causes no harm under normal
operating conditions.
The explanation is as follows. The transmit sigma-delta
modulator in the SCNT1 is RESET whenever a transi-
tion from nonzero data to zero data occurs. It was
designed this way for ease of production testing, so
that the sigma-delta is always initialized to a known
state. This resetting is what causes the glitch. In normal
operation, the nonzero to zero case will never occur,
except when the transceiver is going from an active
state to RESET. In this case, there is a control signal
that grounds the input to the line driver to force it to
transmit 0 V (i.e., forces it into a low-impedance state—
this feature grew out of the ANSI requirements), so the
sigma-delta modulator has no effect in this case.
Thus, the glitch never occurs in normal operation and
should be ignored when observing the pulse output.
This has been confirmed independently at Bellcore
using their test bed that digitizes the chip output under
normal operation, and then reconstructs the pulse
shape using DSP filtering techniques.
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