
Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
28
Lucent Technologies Inc.
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 10. Control Flow State Machine Control—Maintenance/Reserved Bits (Address 06h)
This
register has no effect on device operation if AUTOCTL = 1 (register GR0, bit 3).
Reg
CFR0
R/W
R/W
Bit 7
—
—
Bit 6
—
—
Bit 5
R64T
1
Bit 4
R25T
1
Bit 3
R16T
1
Bit 2
R15T
1
Bit 1
AFRST
1
Bit 0
ILOSS
1
Default State on RESET
Register
CFR0
Bit
0
Symbol
ILOSS
Name/Description
Insertion Loss Test Control.
The insertion loss test mode is initiated
by setting AFRST = 0 and ILOSS = 0, and then setting AFRST = 1.
When enabled, the U-interface transmitter continuously transmits the
sequence SN1. The U-interface receiver remains reset. The U-interface
transceiver performs an internal reset when the ILOSS bit returns to its
inactive state.
0—U-transmitter sends SN1 tone continuously.
1—No effect on device operation (default).
Adaptive Filter Reset.
U-transceiver reset. Assertion of this bit halts U-
interface data transmission and clears adaptive filter coefficients. Dur-
ing AFRST, the U transmitter produces 0 V and has an output imped-
ance of 135
. If the microprocessor interface is being used, the AFRST
bit should be used to place the device in quiet mode for U-interface
maintenance procedures. Assertion of AFRST does not reset the S/T
transceiver, microprocessor register bits, or the U-interface timing re-
covery.
0—U-transceiver reset.
1—No effect on device operation (default).
Transmit Reserved Bits.
Controls R
1, 6
and R
1, 5
in transmit
U-interface data stream.
11—(Default.)
Transmit Reserved Bit.
Controls R
2, 5
in transmit U-interface data
stream.
1—(Default.)
Transmit Reserved Bit.
Controls R
6, 4
in transmit U-interface data
stream.
1—(Default.)
CFR0
1
AFRST
CFR0
3—2
R[16:15]T
CFR0
4
R25T
CFR0
5
R64T