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| 型號(hào)： | T7256A |
| 英文描述： | Compliance with the New ETSI PSD Requirement |
| 中文描述： | 符合新的ETSI PSD的要求 |
| 文件頁(yè)數(shù)： | 35/116頁(yè) |
| 文件大?。?/td> | 1056K |
| 代理商： | T7256A |
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Data Sheet
January 1998
T7256 Single-Chip NT1 (SCNT1) Transceiver
Lucent Technologies Inc.
31
Microprocessor Interface Description
(continued)
Registers
(continued)
Table 13. eoc State Machine Control—Address (Address 09h)
This register has no effect on device operation if AUTOEOC = 1 (register GR0, bit 4).
Reg
ECR0
R/W
R/W
Bit 7
CCRC
1
Bit 6
U2BDLT
1
Bit 5
UB2LP
1
Bit 4
UB1LP
1
Bit 3
DMT
1
Bit 2
A1T
0
Bit 1
A2T
0
Bit 0
A3T
0
Default State on RESET
Register
ECR0
Bit
0—2
Symbol
A[3:1]T
Name/Description
Transmit eoc Address.
000—NT address (default).
111—Broadcast address.
Transmit eoc Data or Message Indicator.
0—Data.
1—Message (default).
U-Interface Loopback of B1 Channel Control.
Control for U-interface
transparent B1 loopback. UB1LP and UB2LP may be enabled concurrent-
ly.
0—B1 channel loopback from U-interface receive to U-interface trans-
mit upstream of data flow matrix.
1—No loopback (default).
U-Interface Loopback of B2 Channel Control.
Control for U-interface
transparent B2 loopback. UB1LP and UB2LP may be enabled concurrent-
ly.
0—B2 channel loopback from U-interface receive to U-interface trans-
mit upstream of data flow matrix.
1—No loopback (default).
Transparent 2B+D Loopback Control.
When activated, this bit causes
a transparent 2B+D loopback from S/T transmitter to S/T receiver at the
device pins (i.e., as close as possible to the S/T-interface) according to
ITU-T I.430 Loop2. Any signals from the TE are ignored during this loop-
back.
0—Transparent 2B+D loopback:
The microprocessor must clear the D-channel echo bit control
(SXE = 0) and data flow matrix (SXB10 = SXB11 = SXB20 = SXB21
= SXD = UXB10 = UXB11 = UXB20 = UXB21 = UXD = 1) for proper
operation of the loopback.
1—No loopback (default).
Corrupt Cyclic Redundancy Check.
Used to corrupt the CRC informa-
tion transmitted at the U-interface.
0—Corrupt CRC generation.
1—Generate correct CRC (default).
ECR0
3
DMT
ECR0
4
UB1LP
ECR0
5
UB2LP
ECR0
6
U2BDLT
ECR0
7
CCRC
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