![](http://datasheet.mmic.net.cn/370000/STDM110_datasheet_16733661/STDM110_715.png)
Samsung ASIC
5-52
STDM110
Compiled Datapath Macrocells
COMPILED MACROCELLS
COMPILED DATAPATH MACROCELLS
Datapath macro cell is a set of n-bit data operators that enables more efficient datapath module design and
implementation. Compiled datapath macro cell creates area-, speed- and power-optimized adders,
subtracters, barrel shifters, and multipliers based on the user specified parameters. It creates a function mod-
el, a timing information for simulation, and a verified hard macro layout.
The followings are the summary of main features of compiled datapath macro cells:
ADVANCED DESIGN TECHNIQUE
All of STDM110 compiled datapath macro cells adopt very advanced design techniques to get optimized per-
formances on the given parameters. Some of those design techniques are as follows:
— Hierarchical double carry select scheme to reduce carry-chain delay
— Transmission gate multiplexing for data shifting
— Allowing pipeline insertion in multiplication
— Primitive standard cell compatible leaf cell layout
— Allowing over-the-cell routing
— Dense datapath module layout generation with topological regularity.
FLEXIBLE DATAPATH MACROCELL DESIGN FLOW
The implementation of datapath module is one of the most critical and important elements in the design of
high performance systems; DSPs, multimedia, graphics, microprocessors and so on. In these systems, the
datapath modules are used much more than other designs and at the same time, datapath module affects
the overall design performances.
The macrocell generation flow is tightly integrated into Apollo, Avant! which is used as a main tool at a full
chip layout step. By supporting an easy-to-use ASIC environment, achieving full custom-like density, perform-
ance, ASIC designers can expect improving productivity. In the design of datapath macro cell, the optimal
module placement of leafcell is a key point to take advantage of inherent regularity in datapaths. An optimal
datapath module placement can maximize density, minimize speed, bus line skew, power consumption and
turn-around time in ASIC design.
The design environment has been developed to support datapath macro cells as shown in below. This flow
is tightly integrated from Verilog, Cadence, to Apollo, Avant!. With the pre-defined leafcell information and
given parameters, the schematic generator gives a Verilog structural netlist of datapath cell and the place-
ment information of used leafcell instances. It enables the mapping of regularity from a logic design into a
standard cell place-and-rout tool. You can get area- and performance-optimized layouts of datapath macro
cells.
Figure 5-3
Datapath Instance Generatin Flow
Leafcell
Parameter
Instance netilst
Instance
Place
Schematic
Apollo