Introduction
1.4 Product Family
Samsung ASIC
1-13
STDM110
To improve the memory performance and to reduce the power consumption, 2-
bank architecture is provided except some memories such as dual-port
synchronousstaticRAM,multi-portasynchronousregisterfileandfirst-infirst-out
memory. In 2-bank architecture, only one bank is activated and the other bank is
in standby mode.
To support various memory shapes which are determined by the floorplan of a
chip design, flexible memory aspect ratios are provided. For certain specific
memory configuration, all types of timing, power and area values are provided by
an automatic datasheet generator.
To easily do interface to layout, the physical abstract data for Silicon Ensemble
and Apollo, called phantom cell or black box, is provided. BIST(Built-In Self-Test)
circuitry is currently available for most of STDM110 compiled memories. BIST
circuits are designed to detect a set of fault types that impact the functionality of
memory and is generated by a softmacro-based BIST generator.
The softmacro-based BIST generator generates both an individual BIST netlist
for each memory and a shared BIST netlist for all memories used in a design.
However, when several memories of the same or the different type area used in
the design, if you generate the individual BIST netlist for each memory, there are
some redundant blocks because the individual BIST netlist has same function. In
thiscase,itwouldbetterusethesharedBISTnetlisttoeliminatesuchredundancy
and reduce area.
1.4.3.2 Compiled Datapath Macrocells
Compiled datapath macro cells include Adder, Barrel Shifter and Multiplier. Adder
performs the adding or adding/subtracting operation on the control of a mode
selection signal. Barrel Shifter makes input data shift or rotate in the left/right
direction. In the shift operation, the vacant bit can be padded with zero, MSB
value, or external data. Multiplier performs the 2's compliment multiplication. One
pipeline stage insertion is available to get a high operating frequency.
They have two output drive strengths, which are equal to the 1X and 2X-Drive in
the primitive cell library. The hard macro cells are built through the Apollo,
placement and routing tool from Avant!. All the leaf cells have the same physical
configuration compatible with the primitive cell library. It allows that any primitive
cell can be used as a bit slice cell in the datapath module design.
We provide two kinds of engineering design services. One is to support additional
compiled datapath macrocells such as ALUs, Comparators, Priority encoders,
Incrementers and Decrementers, and so on. Another is to make hardwired
datapath module design which provides a regular structured layout.