Samsung ASIC
iv
STDM110
Contents
1
Introduction
1.1 Library Description................................................................................................................1-1
1.2 Features................................................................................................................................1-2
1.3 EDA Support .........................................................................................................................1-4
1.4 Product Family ......................................................................................................................1-4
1.4.1 Analog Core Cell.................................................................................................1-4
1.4.2 Internal Macrocells............................................................................................1-12
1.4.3 Compiled Macrocells...........................................................................................1-12
1.4.4 Input/Output Cells ...............................................................................................1-14
1.5 Timings....................................................................................................................................1-16
1.6 Delay Model ............................................................................................................................1-22
1.7 Testability Design Methodology...............................................................................................1-24
1.8 Maximum Fanouts...................................................................................................................1-27
1.9 Packages Capability by Lead Count .......................................................................................1-34
1.10 Power Dissipation..................................................................................................................1-36
1.11 V
DD
/V
SS
Rules and Guidelines..............................................................................................1-39
1.12 Crystal Oscillator Considerations..........................................................................................1-45
2
Electrical Characteristics
DC Electrical Characteristics.........................................................................................................2-1
3
Internal Macrocells
Overview .......................................................................................................................................3-1
Summary Tables ...........................................................................................................................3-2
Logic Cells
AD2DH/AD2/AD2D2/AD2D4.........................................................................................................3-17
AD3DH/AD3/AD3D2/AD3D4.........................................................................................................3-19
AD4DH/AD4/AD4D2/AD4D4.........................................................................................................3-21
AD5/AD5D2/AD5D4......................................................................................................................3-24
ND2DH/ND2/ND2D2/ND2D4........................................................................................................3-27
ND3DH/ND3/ND3D2/ND3D4........................................................................................................3-29
ND4DH/ND4/ND4D2/ND4D2B/ND4D4.........................................................................................3-32
ND5/ND5D2/ND5D4......................................................................................................................3-35
ND6/ND6D2/ND6D4......................................................................................................................3-38