1.11 VDD/VSS Rules And Guidelines
Introduction
STDM110
1-40
Samsung ASIC
The number of VDD1I/VSS1I pad pairs required for a design can be calculated from the following expression:
The number of VDD1I/VSS1I pad pairs =
where,
G = The core (excluding hard macro blocks) size in the gate counts
S = The switching ratio (typically = 0.1)
F = Operating frequency (MHz)
Pi = Characterized current for the i-th hard macro block (mA/MHz)
Fi = Operating frequency for the i-th hard macro block (MHz)
I
em
= Current limit per VDD/VSS pad pairs based on ElectroMigration
rule (80mA)
For reliable device operation and minimize IR voltage drop, minimum number of VDD1I/VSS1I power pad pairs is
4.
Extra power may be needed for the demanding high power macro blocks (SRAM, analog block...).
1.11.3 VDD2P/VSS2P (VDD3P/VSS3P) ALLOCATION GUIDELINES.
These guidelines ensure that an adequate input threshold voltage margin is maintained during a switching.
The number of VDD2P/VSS2P (VDD3P/VSS3P) pads required for a design can be calculated from the following
expression:
In above expression,
I
eq_p
=
∑
(Average current of input/output buffers and bi-direction pre-drivers at maximum operational I/O
frequency) [mA] (Refer Table 1-11)
Table 1-11.
Input Buffer Type
Ieq_p (mA)
Output Pre-Driver Type
2.5V Interface
CMOS
0.35
Driver
B6–8
0.27
0.25
CMOS Schmitt
0.36
Tristate
T6–8
0.36
0.35
B1–4
0.14
0.14
B10–12
0.41
0.35
T1–4
0.24
0.25
T10–12
0.53
0.45
Ieq_p (mA)
Normal
Slew rate
0.001
0.0062 S 0.0044
+
(
)
×
G F
Pi Fi
(
)
i
N_macro
∑
+
×
l
em
round up
–
Number_ of_VDD2P/VSS2P(VDD3P/VSS3P) pairs
eq_p
l
em
l
–
=
where
N_input is the number of input buffers used,
N_output is the number of output buffers used,
N_bi is the number of bi-directional buffers used,
F is the operating frequency in MHz,
S
out
is the output mode ratio of bi-directional buffers (typically 0.5),
I
em
= Current limit per VDD/VSS pad pairs based on electromigration rule. (80mA)
I
eq_p
I
eq_p_in
F
i
100
×
i
N_input
∑
I
j_eq_p_out
F
j
100
×
j
N_output
∑
I
k_eq_p_in
F
k
100
×
1 S
out
–
(
)
k
N_bi
∑
I
k_eq_p_out
F
k
100
×
S
out
×
+
+
+
=