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Introduction
1.4 Product Family
Samsung ASIC
1-11
STDM110
technology to synthesize a higher frequency on-chip clock using the system clock
as a reference.
6) Deskew clock: Multiple chips on a printed circuit board or cores of different
sizes within a single system on a chip experience clock skew. By using PLL or
DLL technology to shift the phase of the reference clock within each chip or core,
designers can minimize skew tune a system to perform up its potential.
7) Duty Ratio: the percentage of the period that the output is in a high state.
8) Output frequency range: The maximum output frequency range minus the
minimum output frequency that is produced with an input signal for which the cell
specifications still apply.
Customer Service
Samsung provides a full custom support for our customers need of analog cores.
Samsung's worldwide sales offices and representatives give our customers a
first-hand support for analog cores. And if needed, Samsung engineers are pre-
pared to provide a fully customized total solution to satisfy our customers.
Technical Support
If our customers want to develop mixed-signal products, Samsung provides all
technical support to meet customers needs. Mixed-signal design is quite different
from pure logic design in terms of circuit design, techniques, layout and test meth-
odology. Thus Samsung provides a successful technical guide and firmly support
for all development steps.
Definition of Analog Core Data Sheet Types
Each product developed by Samsung will be supported by technical literature
where the data sheets progress through the following levels of refinement
1. Core Preview
Describes the main features and specifications for core that is under
development. Some specifications such as exact pin-outs may not be finalized at
time of publication.The purpose of this document is to provide customers with
advance product planning information.
2. Preliminary Datasheet
This is the first document completely describing a new core. It contains an
features, application, timing diagram, theory of operation, core pin information,
test guide, layout guide and AC/DC electrical information. This data sheet are
based on prototype silicon performance and on worst case simulation
models.The purpose of this data sheet is to provide ASIC customer with technical
information sufficiently detailed to guarantee that they can safely begin active
development.
3.Final Data sheet
Thisisanupdatedversionofpreliminarydatasheetreflectingactualperformance
of the final silicon. Updates include tighter specifications, more min. and max.
values. The purpose of this data sheet is to communicate the confirmed
performance of cores which have passed qualification, been fully characterized.