參數(shù)資料
型號(hào): ST20GP6
英文描述: MAX 7000 CPLD 256 MC 208-RQFP
中文描述: GPS處理器
文件頁數(shù): 92/116頁
文件大?。?/td> 1107K
代理商: ST20GP6
ST20-GP1
92/116
15.4.3 Direct DMA protocol
In this mode the PLink becomes an unsynchronized (i.e. direct action) bus. The
PlinknotAck
output still behaves as if it were acknowledging a real transfer. The
PlinknotReq
signal has no
effect in this mode of operation. In this mode
PlinknotAck
is active high. The initial (inactive) state
of the pin is low.
Direct mode output
To drive the output pins the PLink must be programmed to make a single byte DMA. If more than
one byte is output, the PLink will continue to drive the output pins as fast as the output DMA can
feed the data, i.e. once every 8 or more system clock cycles, until the correct number of bytes have
been output. The sequence of events for a single byte read is outlined below. When configured as
an output the drivers are always driven.
1
The PLink forces the
PlinknotAck
pin high. The output pins are then driven with the new
data and the
PlinknotAck
pin is forced low.
2
The output data remains static and driven to the pads until either a new value is written as
output or until the link direction is changed. If the PLink returns to direct output mode, the
old data is once again driven to the pads.
Note: At reset
PlinknotAck
is a logic one, appearing to the outside world as an ‘a(chǎn)cknowledge’.
External logic will assume that the data has been read. Therefore after programming the PLink to
direct mode the
PlinknotAck
output falls.
Direct mode input
To read the input pins the PLink must be programmed to make a single byte DMA. The sequence
of events for a single byte read is outlined below.
1
The PLink forces the
PlinknotAck
pin high. The input pins are then read and the
Plinkno-
tAck
pin is forced low.
Figure 15.3 Direct DMA protocol
ST20 Output
PlinknotAck
PlinkData0-7
ST20 Input
PlinknotAck
PlinkData0-7
valid data
相關(guān)PDF資料
PDF描述
ST25C02AB1 IC FLEX 6000 FPGA 16K 144-TQFP
ST25C02AB6 Stratix FPGA 25K FBGA-672
ST25C02AM1 IC ACEX 1K FPGA 100K 208-PQFP
ST25C02AM6 Cyclone II FPGA 20K FBGA-256
ST25C04ML1 IC FLEX 6000 FPGA 24K 144-TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST20-GP6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR
ST20GP6CT33S 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR
ST20GP6CX33S 功能描述:射頻無線雜項(xiàng) GPS Processor RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel
ST20GP6CX33STR 功能描述:射頻無線雜項(xiàng) GPS Processor RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel
ST20GP6X33S 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:GPS PROCESSOR