參數(shù)資料
型號: ST20GP6
英文描述: MAX 7000 CPLD 256 MC 208-RQFP
中文描述: GPS處理器
文件頁數(shù): 59/116頁
文件大?。?/td> 1107K
代理商: ST20GP6
ST20-GP1
59/116
status of the lock and stall bits. Table 9.6 shows the format of the
EMIConfigStatus
register.
EMIConfigStall register
The
EMIConfigStall
register can be used to stall the EMI. When set it prevents the EMI from
accepting further requests from the CPU or communications subsystems. Its main use is intended
to be in systems which anticipate turning the power off; the EMI must be inactive during such an
event, otherwise battery backed memory may be corrupted.
This register, once set, can only be cleared by resetting the ST20-GP1.
9.6
Reset and bootstrap behavior
Table 9.8 shows the state of the EMI signals during reset.
MemAddr2-19
are driven with a copy of
the value on the internal memory bus2-19.
Table 9.9 shows the configuration values for all banks during and after reset. If the
BootSource0-1
pins indicate that the ST20-GP1 will boot from ROM, the
BusWidth
is set to the correct value as
the ST20-GP1 comes out of reset.
EMIConfigStatus
EMI base address + #20
Read only
Bit
0
1
2
3
4
5
31:6
Bit field
WrittenBank0
WrittenBank1
WrittenBank2
WrittenBank3
WriteLock
MemStall
Function
Bank 0 configuration has been written to using a devsw instruction.
Bank 1 configuration has been written to using a devsw instruction.
Bank 2 configuration has been written to using a devsw instruction.
Bank 3 configuration has been written to using a devsw instruction.
EMIConfigData0-3
registers are write protected.
EMIConfigStall
has been set.
Reserved
Table 9.6
EMIConfigStatus
register format
EMIConfigStall
EMI base address + #30
Write only
Bit
Bit field
Function
0
EMIStall
When set, this bit prevents the arbiter from granting any more accesses to the
memory subsystem.
Table 9.7
EMIConfigStall
register format
Pins
Value
MemAddr2-19
MemAddr1
notMemCE0-3
notMemOE0-1
notMemWB0-1
MemData0-15
Table 9.8 EMI signal values during reset
Valid
High
All high
All high
All high
High impedance
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