參數(shù)資料
型號: ST20GP6
英文描述: MAX 7000 CPLD 256 MC 208-RQFP
中文描述: GPS處理器
文件頁數(shù): 58/116頁
文件大?。?/td> 1107K
代理商: ST20GP6
ST20-GP1
58/116
9.5
EMI configuration registers
Configuration parameters are stored in registers which are mapped into the device address space.
They may be accessed using devsw(device store word) and devlw(device load word) instructions.
The base addresses for the EMI registers are given in the Memory Map chapter.
EMIConfigData0-3 registers
The
EMIConfigData0-3
registers contain configuration data for each of the EMI banks. The format
of each of the
EMIConfigData0-3
registers is identical and is shown in Table 9.4.
EMIConfigLock register
The
EMIConfigLock
register is provided to write protect the
EMIConfigData0-3
registers (further
writes to these registers are ignored). This bit is set by performing a devsw instruction to the given
address; the write data is ignored.
This register, once set, can only be cleared by resetting the ST20-GP1.
EMIConfigStatus register
The
EMIConfigStatus
register is provided to indicate which registers have been written to and the
EMIConfigData0-3
EMI base address + #00, #04, #08, #0C
Read/Write
Bit
Bit field
Function
Units
0
3:1
4
MemWaitEnable
DataDriveDelay
BusWidth
Enables the
MemWait
pin.
Drive delay of data bus for writes.
Bus width of the bank (8 or 16 bits).
BusWidth
0
1
Duration of the external access.
Duration bus release time.
Delay from access start to
notMemCE
falling edge.
Delay from
notMemCE
rising edge to end of access.
Delay from access start to
notMemOE
falling edge.
Delay from access start to
notMemWB
falling edge.
Delay from
notMemWB
rising edge to end of access.
Reserved
-
Phases
Bank width
16 bits
8 bits
-
8:5
10:9
14:11
18:15
22:19
26:23
30:27
31
AccessDuration
BusReleaseTime
CEe1Time
CEe2Time
OEe1Time
WBe1Time
WBe2Time
Cycles
Cycles
Phases
Phases
Phases
Phases
Phases
-
Table 9.4
EMIConfigData0-3
register format - 1 per bank
EMIConfigLock
EMI base address + #10
Write only
Bit
Bit field
Function
0
ConfigLock
When set, the
EMIConfigData0-3
registers are read only.
Table 9.5
EMIConfigLock
register format
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